Intel Patents
Application number: 20150248292
Abstract: Technologies are presented that optimize data processing cost and efficiency. A computing system may comprise at least one processing element; a memory communicatively coupled to the at least one processing element; at least one compressor-decompressor communicatively coupled to the at least one processing element, and communicatively coupled to the memory through a memory interface; and a cache fabric comprising a plurality of distributed cache banks communicatively coupled to each other, to the at least one processing element, and to the at least one compressor-decompressor via a plurality of nodes. In this system, the at least one compressor-decompressor and the cache fabric are configured to manage and track uncompressed data of variable length for data requests by the processing element(s), allowing usage of compressed data in the memory.
Type:
Application
Filed:
February 28, 2014
Issued:
September 3, 2015
Assignee:
Intel Corporation
Inventors:
Altug Koker, Hong Jiang, James M. Holland
Patent number: 9125121
Abstract: A communication networks including a plurality of small cell providing air interface infrastructure functionality is provided. Aspects of the present disclosure relate to the management of inter-small cell communication in accordance multiple air interfaces supported within individual small cells. Additionally, aspects of the present disclosure relate to the management of intra-small cell communication in accordance with communication networks implementing multiple small cells. In other aspects, small cells coordinate handovers through the use of a controller, or by leveraging wireless connections created between the small cells. In further aspects, the small cells enable the utilization of multiple air interface standards within a small cell.
Type:
Grant
Filed:
September 4, 2012
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Jacob Sharony, Khurram Parviz Sheikh
Patent number: 9122169
Abstract: Improved mask layout patterns are described for closely spaced primitives in phase shift photolithography masks. In one example, at least a portion of a photolithography mask layout is decomposed into primitives. Jogs are identified from among the primitives, the jogs being characterized by three adjacent corners. E-fields are determined for the identified jogs and are applied to synthesize an electric field at a substrate. The mask layout is corrected using the synthesized electric field and a printed wafer pattern is calculated.
Type:
Grant
Filed:
December 29, 2011
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Bin Hu, Vivek K. Singh, Sungwon Kim, Chulwoo Oh, Mehmet E. Yavuz
Patent number: 9121768
Abstract: A thermal sensor is provided that includes a front-end component, an analog-to-digital converter and a digital backend. The front-end component including an array of current sources, a dynamic element matching (DEM) device, an analog chopper and two diodes to sense temperatures on the die. The front-end component to provide analog signals at two output nodes based on currents through the two diodes. The analog-to-digital converter to receive the analog signals from the front-end component and to provide an output signal. The digital backend to receive the output signal from the analog-to-digital converter and to provide a calculated temperature.
Type:
Grant
Filed:
December 16, 2011
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Arijit Raychowdhury, Hasnain Lakdawala, Yee (William) Li, Greg Taylor, Soumyanath Krishnamurthy
Patent number: 9122475
Abstract: A mask generating instruction is executed by a processor to improve efficiency of vector operations on an array of data elements. The processor includes vector registers, one of which stores data elements of an array. The processor further includes execution circuitry to receive a mask generating instruction that specifies at least a first operand and a second operand. Responsive to the mask generating instruction, the execution circuitry is to shift bits of the first operand to the left by a number of times defined in the second operand, and pull in a bit of one from the right each time a most significant bit of the first operand is shifted out from the left to generate a result. Each bit in the result corresponds to one of the data elements of the array.
Type:
Grant
Filed:
September 28, 2012
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Mikhail Plotnikov, Igor Ermolaev, Andrey Naraikin, Robert Valentine
Patent number: 9122467
Abstract: In one embodiment, the present invention includes a primary voltage regulator to couple a regulated voltage to a processor via a supply line. This regulator includes a multi-phase controller to provide the regulated voltage in multiple phases and to provide a maximum current output sufficient to meet a thermal design power (TDP) of the processor. In addition, an auxiliary voltage regulator may be configured to provide an excess current to the processor via the supply line for a time limited duration, e.g., based on the supply line state. Other embodiments are described and claimed.
Type:
Grant
Filed:
March 5, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
James S. Dinh, Robert D. Wickersham, Daniel Kingsley, Edward L. Payton
Patent number: 9125103
Abstract: Embodiments of the present disclosure describe techniques and configurations for handling a wait time in a wireless communication network when the network is determined to be congested. An apparatus may include computer-readable media having instructions and one or more processors coupled with the computer-readable media and configured to execute the instructions to send a radio resource control request message to a wireless network controller, receive a response message including an extended wait time value, determine upon receipt of the response message whether a back-off timer associated with the apparatus is running, and determine whether to start the backoff timer with the received extended wait time value based at least in part on the determination of whether the back-off timer is running and the received wait time value is integrity protected.
Type:
Grant
Filed:
June 13, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventor:
Vivek Gupta
Patent number: 9122377
Abstract: An application interoperation method includes: maintaining a handler table including data type information, function information and calling information associated with each application installed in a portable device; receiving input information on a menu key of the portable device, from a user, while a first application is active; extracting, in response to the receipt of the input information, at least one function information associated with data type information, which is being processed or requested by the first application, from the handler table; dynamically generating a menu including the extracted function information to provide the user with the generated menu; receiving selection information on particular function information among the provided menu, from the user; and identifying calling information associated with the selected particular function information by referring to the handler table and executing a second application based on the identified calling information.
Type:
Grant
Filed:
April 8, 2014
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Yun Ho Jeon, Eun Ah Kim, Su Jin Kim
Patent number: 9122464
Abstract: Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state.
Type:
Grant
Filed:
December 22, 2011
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Inder M. Sodhi, Efraim Rotem, Alon Naveh, Sanjeev S. Jahagirdar, Varghese George
Patent number: 9122577
Abstract: A method and apparatus for matching parent processor address translations to media processors'address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
Type:
Grant
Filed:
November 14, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Brent S. Baxter, Prashant Sethi, Clifford D. Hall, William H. Clifford
Patent number: 9123724
Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
Type:
Grant
Filed:
December 19, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
Patent number: 9122624
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
Type:
Grant
Filed:
October 18, 2014
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
Patent number: 9122632
Abstract: Methods and apparatus relating to programmable power performance optimization for graphics cores are described. In one embodiment, the first frame of a scene is analyzed. It is then determined whether to optimize one or more operations, to be performed on one or more frames of the scene, based on the second frame of the scene and an idle status of one or more subsystems of a processor. And, one or more optimization operations are performed on a third frame of the scene based on the determination of whether to optimize the one or more operations. Other embodiments are also disclosed and claimed.
Type:
Grant
Filed:
June 30, 2012
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventor:
Linda L. Hurd
Patent number: 9122290
Abstract: A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential amplifier having a first input, a second input and an output. The circuit further includes a CTAT circuit configured to generate a CTAT voltage at an output thereof. A first resistor is coupled between the output of the differential amplifier and the output of the CTAT circuit. Further, the first resistor is connected between the first input and the second input of the differential amplifier.
Type:
Grant
Filed:
March 15, 2013
Issued:
September 1, 2015
Assignee:
Intel Deutschland GmbH
Inventor:
Matthias Eberlein
Patent number: 9122780
Abstract: Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for tracking per-virtual machine (“VM”) resource usage independent of a virtual machine monitor (“VMM”). In various embodiments, a first logic unit may associate one or more virtual central processing units (“vCPUs”) operated by one or more physical processing units of a computing device with a first VM of a plurality of VMs operated by the computing device, and collect data about resources used by the one or more physical processing units to operate the one or more vCPUs associated with the first VM. In various embodiments, a second logic unit of the computing device may determine resource-usage by the first VM based on the collected data. In various embodiments, the first and second logic units may perform these functions independent of a VMM of the computing device.
Type:
Grant
Filed:
June 20, 2012
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Mahesh S. Natu, Anil S. Keshavamurthy, Alberto J. Munoz, Tessil Thomas
Patent number: 9122811
Abstract: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.
Type:
Grant
Filed:
August 16, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Michael Klinglesmith, Mohan Nair, Joseph Murray
Patent number: 9122945
Abstract: A method for processing data includes identifying a time signature of an infra-red (IR) beacon. Image data associated with the IR beacon is identified using the time signature.
Type:
Grant
Filed:
November 5, 2012
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
David J. Cowperthwaite, Bradford H. Needham
Patent number: 9122815
Abstract: In one embodiment, the present invention includes method for entering a credit initialization state of an agent state machine of an agent coupled to a fabric to initialize credits in a transaction credit tracker of the fabric. This tracker tracks credits for transaction queues of a first channel of the agent for a given transaction type. The agent may then assert a credit initialization signal to cause credits to be stored in the transaction credit tracker corresponding to the number of the transaction queues of the first channel of the agent for the first transaction type. Other embodiments are described and claimed.
Type:
Grant
Filed:
July 9, 2014
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Sridhar Lakshmanamurthy, Robert P. Adler, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray, Rohit R. Verma
Patent number: 9123088
Abstract: In accordance with some embodiments, partial rendering of non-changing or slowly changing frame tiles allows the graphics processing unit to spend less time processing non-changing or slowly changing portions of each frame, saving power and creating more room for performance in some embodiments.
Type:
Grant
Filed:
July 31, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Nikos Kaburlasos, Eric C. Samson, Robert B. Taylor
Patent number: 9123167
Abstract: A graphics engine with shader unit thread serializing and instance unrolling functionality that executes multi-threaded shader logic in a single hardware thread is described. Hardware accelerated tessellation functionality is implemented utilizing programmable pipeline stages that allow custom, runtime configuration of graphics hardware utilizing programs compiled from a high level shader language that are executed using one or more shader execution cores. In one embodiment, multiple shader unit program threads are serialized to run in one hardware thread to allow a greater number of instructions to be executed on the shader cores and preserve hardware threads for primitive processing by other shader units.
Type:
Grant
Filed:
September 29, 2012
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Yunjiu Li, Michael Green
Patent number: 9123349
Abstract: Methods and apparatus to provide speech privacy are disclosed. An example method includes forming a sampling block based on a first received audio sample, the sampling block representing speech of a user, creating, with a processor, a mask based on the sampling block, the mask to reduce the intelligibility of the speech of the user, wherein the mask is created by converting the sampling block from a time domain to a frequency domain to form a frequency domain sampling block, identifying a first peak within the frequency domain sampling block, demodulating the frequency domain sampling block at the first peak to form a first envelope of the sampling block, distorting the first envelope to form a first distorted envelope, and emitting an acoustic representation of the mask via a speaker.
Type:
Grant
Filed:
September 28, 2012
Issued:
September 1, 2015
Assignee:
INTEL CORPORATION
Inventor:
Rafael de la Guardia Gonzales
Patent number: 9123410
Abstract: The present disclosure relates to a memory controller. The memory controller may include a memory controller module configured to identify a target word line in response to a memory access request, the target word line included in a cross-point memory, the memory controller module further configured to perform a memory access operation on a memory cell of the cross-point memory, the memory cell coupled between the target word line and a bit line; and a word line control module configured to float at least one adjacent word line adjacent the target word line, the floating comprising decoupling the at least one adjacent word line from at least one of a first voltage source or a second voltage source. In some embodiments, the floating reduces an effective capacitance associated with the target word line during the memory access operation.
Type:
Grant
Filed:
August 27, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Hernan A. Castro, Jeremy M. Hirst, Eric Carman
CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
Patent number: 9123567
Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
Type:
Grant
Filed:
December 19, 2011
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
Patent number: 9122335
Abstract: An article, device and method may detect a touch of a human hand on an interactive area of a user interface display of a mobile device. A non-interactive area may be displayed on the user interface display in at least a location of the touch of the human hand.
Type:
Grant
Filed:
March 18, 2014
Issued:
September 1, 2015
Assignee:
INTEL CORPORATION
Inventor:
Bradley Corrion
Patent number: 9123732
Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.
Type:
Grant
Filed:
September 28, 2012
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Sandeep B. Sane, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
Patent number: 9123727
Abstract: An airgap interconnect structure with hood layer and methods for forming such an airgap interconnect structure are disclosed. A substrate having a dielectric layer with a plurality of interconnects formed therein is provided. Each interconnect is encapsulated by a barrier layer. A hardmask is formed on the dielectric layer and patterned to expose the dielectric layer between adjacent interconnects where an airgap is desired. The dielectric layer is etched to form a trench, wherein the etching process additionally etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect. A hood layer is electrolessly plated onto an exposed portion of the top surface and the exposed portion of the side surface to reseal the interconnect. A gap-sealing dielectric layer is formed over the device, sealing the trench to form an airgap.
Type:
Grant
Filed:
December 29, 2011
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventor:
Kevin Fischer
Patent number: 9124084
Abstract: An electrical overstress (EOS) protection circuit that at least partially neutralizes or compensates for undershoot and overshoot in first and second signals that are communicated using differential signaling, such as with USB communications. For an undershoot, the EOS protection circuit injects charge into pads that receive the first and second signals. For an overshoot, the EOS protection circuit drains charge from the pad that receives the second signal and injects charge into the pad that receives the first signal.
Type:
Grant
Filed:
November 3, 2011
Issued:
September 1, 2015
Assignee:
INTEL CORPORATION
Inventor:
Suhas Vishwasrao Shinde
Patent number: 9123790
Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.
Type:
Grant
Filed:
December 28, 2011
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Ravi Pillarisetty, Benjamin Chu-Kung, Willy Rachmady, Van H. Le, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Han Wui Then, Marko Radosavljevic
Patent number: 9123706
Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.
Type:
Grant
Filed:
December 21, 2011
Issued:
September 1, 2015
Assignee:
INTEL CORPORATION
Inventors:
Daniel J. Zierath, Shaestagir Chowdhury, Chi-Hwa Tsang
Patent number: 9124229
Abstract: An amplifier, including a voltage-to-current converter (V2I) to control an output current based on an input voltage, resistive degeneration circuitry to reduce baseband gain of the voltage-to-current converter, capacitive degeneration circuitry to increase passband gain of the voltage-to-current converter, and impedance control circuitry to compensate for negative input impedance of the capacitive degeneration circuitry. The V2I may include series-connected complimentary V2Is. The impedance control circuitry may include resistive negative feedback to provide a real part of input impedance, which may increase a frequency range for which the amplifier is linear. Capacitive degeneration and associated phase compensation may increase a frequency range for which the resistive feedback is negative. The amplifier may be configured as a single-input/single-output system and/or as a differential system.
Type:
Grant
Filed:
March 13, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Viatcheslav I. Suetinov, Keith Pinson, Nicholas P. Cowley
Patent number: 9125101
Abstract: A technique for setting the transmission powers of individual D2D (device-to-device) transmitters using a distributed power control technique is described. Each individual D2D transmitter learns the interference levels that it imposes on an eNB (evolved Node B) and on D2D receivers other than its partner D2D receiver. The D2D transmitter is then able to adjust its transmission power accordingly. Such managing of interference temperature via distributed power control enables the network to maximize its reuse of time-frequency resources.
Type:
Grant
Filed:
March 8, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Shilpa Talwar, Namyoon Lee
Patent number: 9124455
Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.
Type:
Grant
Filed:
September 24, 2014
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Su Wei Lim, Ronald W. Swartz, Yueming Jiang, Hooi Kar Loo, Athourina Gevergiz, Bruce A. Tennant, Yick Yaw Ho, Poh Thiam Teoh, Jennifer Chin, Hui Shi
Patent number: 9124457
Abstract: Some demonstrative embodiments include devices, systems and/or methods of equalizing received wireless communication signals. For example, a device may include a pre-decoding equalizer to determine a plurality of filter weights by applying both a blind-equalization and a least-mean-squares (LMS) equalization to a wireless communication signal received over a wireless communication channel; a channel estimator to estimate a channel frequency response of the channel based on the filtering weights; and a turbo-equalization scheme including a decoder to decode the wireless communication signal and a turbo equalizer to equalize the decoded wireless communication signal using the estimated channel frequency response.
Type:
Grant
Filed:
March 30, 2011
Issued:
September 1, 2015
Assignee:
INTEL CORPORATION
Inventors:
Evgeny Vasilievich Pustovalov, Evgeny Alexandrovitch Bakin, Grigory Sergeevich Evseev, Andrey Mihailovich Turlikov
Patent number: 9124503
Abstract: Technologies for managing congestion of a communication channel includes a network device for receiving a network packet from a computing device destined for another computing device, analyzing network traffic flows over a communication channel established between the network device and an upstream network device, and determining whether the communication channel is congested as a function of the network traffic flows. Such technologies may also include storing the received packet in a local storage in response to determining that the communication channel is congested, transmitting an acknowledgement packet to the computing device in response to storing the received network packet local storage, and transmitting the stored network packet to the upstream network device in response to determining that the communication channel is no longer congested.
Type:
Grant
Filed:
March 14, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Sanjay Rungta, Dileep K. Basam
Patent number: 9124392
Abstract: Disclosed embodiments may include an apparatus having one or more processors coupled to one or more computer-readable storage media. The one or more processors may be configured to transmit and/or receive channel state information reference signal (CSI-RS) resource configuration information, demodulation reference signals (DM-RS), uplink sounding reference signals (SRS), and power control parameters to support uplink coordinated multi-point (CoMP) operations. Other embodiments may be disclosed.
Type:
Grant
Filed:
November 17, 2014
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Debdeep Chatterjee, Kamran Etemad, Rongzhen Yang, Jong-Kae Fwu, Apostolos Papathanassiou
Patent number: 9124421
Abstract: This disclosure is directed to data prioritization, storage and protection in a vehicular communication system. A black box (BB) in a vehicle may receive data from an on-board unit (OBU) and a vehicular control architecture (VCA). The OBU may interact with at least one RSU that is part of an intelligent transportation system (ITS) via at least two channels, at least one of the at least two channels being reserved for high priority messages. The OBU may transmit ITS data to the BB via a secure communication channel, which may be stored along with vehicular data received from the VCA in encrypted form. In response to a request for data, the BB may authenticate a requesting party, determine at least part of the stored data to which the authenticated party is allowed and sign the at least part of the stored data before providing it to the authenticated party.
Type:
Grant
Filed:
December 4, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Meiyuan Zhao, Christian Maciocco, Shilpa Talwar, Jessie Walker
Patent number: 9124441
Abstract: Various embodiments for remote presentation of an interface of a computing device, such as a PC, are described herein. In particular, in various illustrated embodiments, a local device such as a Digital Media Adapter (DMA), mobile device, cellular telephone, etc. may be used to receive input from a remote control, where the local device provides human perceptible feedback, such as a sound, visual response, etc., responsive to use of the remote control. In some embodiments, the local device may contain a memory or cache for locally storing particular feedback data for human perceptible feedback. In various embodiments, a communication protocol is provided for storing, triggering, deleting, etc. feedback data in the memory or cache. Other embodiments may be disclosed or claimed.
Type:
Grant
Filed:
October 6, 2009
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Ylian Saint-Hilaire, Bryan Y. Roe, Nelson F. Kidd
Patent number: 9124257
Abstract: A digital clock placement engine has circuitry that adjusts a duty cycle of a clock signal and adjusts the locations of the rising/falling edges of the clock signal for purposes of data sampling or other operations. In a forwarded-clock interface implementation, a clock signal is received along with a data signal, and the received clock signal may be distorted to due various factors. To enable the received data signal to be sampled correctly, the clock placement engine generates a recovered clock signal having rising and falling edges that are placed/timed between the rising and falling edges of the received clock signal.
Type:
Grant
Filed:
December 29, 2011
Issued:
September 1, 2015
Assignee:
INTEL CORPORATION
Inventors:
Jayen J. Desai, Erin Francom, Matthew Peters
Patent number: 9124316
Abstract: A transmit circuit includes an envelope tracker configured to determine an envelope of a transmit signal and provide bias information based on the determined envelope of the transmit signal. The transmit circuit further includes a power amplifier configured to generate an RF output signal based on the transmit signal, a bias provider configured to provide a bias for the power amplifier based on the bias information, and an impedance determinator configured to determine a measure of a load impedance of a load coupled to an output of the power amplifier. The envelope tracker is configured to adapt the bias information based on the measure of the load impedance.
Type:
Grant
Filed:
May 9, 2014
Issued:
September 1, 2015
Assignee:
Intel Mobile Communications GmbH
Inventor:
Andreas Langer
Patent number: 9124595
Abstract: A modem device may be provided. The modem device may include: a transceiver structure configured to transmit and receive data using at least one of a plurality of communication technologies; a memory configured to store a profile, the profile including or being information specifying a configuration of the transceiver structure for each communication technology of the plurality of communication technologies; and an application processor interface, wherein the modem device is configured to receive from the application processor a command for configuring the transceiver structure through the application processor interface. The command may include or may be an instruction to the modem device to configure the transceiver structure according to the profile.
Type:
Grant
Filed:
September 17, 2012
Issued:
September 1, 2015
Assignee:
Intel Deutschland GmbH
Inventor:
Jerome Parron
Patent number: 9124635
Abstract: Sensor data may be filtered in a secure environment. The filtering may limit distribution of the sensor data. Filtering may modify the sensor data, for example, to prevent identification of a person depicted in a captured image or to prevent acquiring a user's precise location. Filtering may also add or require other data use controls to access the data. Attestation that a filter policy is being applied and working properly or not may be provided as well.
Type:
Grant
Filed:
November 30, 2012
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Scott H. Robinson, Jason Martin, Howard C. Herbert, Michael LeMay, Karanvir Ken S. Grewal, Keith L. Shippy, Geoffrey Strongin
Patent number: 9125091
Abstract: Technology is discussed for self-optimization approaches within wireless networks to optimize networks for energy efficiency, load capacity, and/or mobility, together with new, supporting channel state measurements and handover techniques. New, Channel State Information-Reference Signals (CSI-RSs) for yet-to-be-configured Cell-IDentifications (Cell-IDs) can be used to determine whether adjacent transmission cells can provide coverage for transmission cells that can be switched off for energy efficiency during formation of a Single Frequency Network (SFN). New approaches are also discussed to facilitate mobility within such a network. The new CSI-RSs and mobility approaches can also be used to split up such a SFN when changing load demands so require. Additionally, such new approaches can be used to create a SFN with a common Cell-ID where high mobility is required, such as near a roadway, and to break it up where high capacity is required, such as during a period of traffic congestion.
Type:
Grant
Filed:
January 4, 2013
Issued:
September 1, 2015
Assignee:
INTEL CORPORATION
Inventors:
Youn Hyoung Heo, Yujian Zhang, Huaning Niu, Yuan Zhu, Debdeep Chatterjee, Jong-Kae Fwu, Hujun Yin
Patent number: 9124577
Abstract: A method for assembling authorization certificate chains among an authorizer, a client, and a third party allows the client to retain control over third party access. The client stores a first certificate from the authorizer providing access to a protected resource and delegates some or all of the privileges in the first certificate to the third party in a second certificate. The client stores a universal resource identifier (URI) associated with both the first certificate and the third party and provides the second certificate and the URI to the third party. The third party requests access to the protected resource by providing the second certificate and the URI, without knowledge or possession of the first certificate. When the authorizer accesses the URI, the client provides the first certificate to the authorizer, so that the client retains control over the third party's access.
Type:
Grant
Filed:
September 16, 2014
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventor:
Victor B. Lortz
Patent number: 9124673
Abstract: Technology for reducing delay in data streaming at a wireless device while improving re-buffering and video quality is disclosed. A missing data segment can be detected based on an out-of-order data segment being received in a plurality of data segments from a network element in a wireless network. A fake acknowledgement (ACK) can be sent to the network element in the wireless network, based on the context information, acknowledging that the missing data segment was received at the wireless device. The out-of-order data segment without the missing data segment can be provided for display at the wireless device.
Type:
Grant
Filed:
September 30, 2013
Issued:
September 1, 2015
Assignee:
INTEL IP CORPORATION
Inventors:
Vallabhajosyula S. Somayazulu, Sangeetha Siddegowda, Wu-Chi Feng, Hassnaa Moustafa, Muthaiah M. Venkatachalam, Danny Moses
Patent number: 9124814
Abstract: A support for image processing is provided, comprising: (a) detecting respective face regions from images consecutively photographed for a first person at predetermined time intervals by an image pickup unit to display images of the face regions detected in relation to the first person in a first region of a screen, and providing a user interface for indicating that a specific face image is selected from the face images of the first person displayed in the first region; (b) additionally displaying the specific face image through a second region adjacent to the first region; and (c) displaying a synthesized image using the specific face image as a representative face of the first person, when the specific face image displayed through the second region is selected.
Type:
Grant
Filed:
February 25, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Daesung Kim, Jaihyun Ahn
Patent number: 9125000
Abstract: Described herein are techniques related to managing mobile applications (“apps”) of a mobile device based, at least in part, upon the determined location of the device. The techniques described herein are especially suited for situations where the present location differs from the locations associated with particular apps that are already installed on the mobile device. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
Type:
Grant
Filed:
December 14, 2012
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Anthony G. LaMarca, Kirk W. Skeba, Jaroslaw J. Sydir
Patent number: 9124940
Abstract: In some embodiments a wireless access point receives digital television content. The digital television content is transmitted in a wireless manner over a wireless network of the wireless access point. The wireless access point may be integrated into a television that redistributes the digital television content. Other embodiments are claimed.
Type:
Grant
Filed:
October 4, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventor:
Ramesh Pendakur
Patent number: 9124972
Abstract: The present invention guides a talker into a narrow sensitivity region by providing a light that is only visible when the talker's eyes are just above the sensitivity region of a microphone. When the talker keeps the light within his sight while speaking, there is no wavering problem. If the talker cannot see the light, then he is outside the sensitivity region and is alerted to a potential wavering problem by not seeing the light. In this way, the present invention takes advantage of the fact that the talker's eyes are located in close proximity to his mouth. In addition, high frequencies emanating from the mouth are highly directional and applications with speech input, such as speech recognition, function better when these high frequencies are available for analysis.
Type:
Grant
Filed:
December 18, 2001
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventor:
David L. Graumann
Patent number: 9124889
Abstract: A decoder adapted to generate an intermediate decoded version of a video frame from an encoded version of the video frame, determine either an amount of high frequency basis functions or coefficients below a quantization threshold for at least one block of the video frame, and generate a final decoded version of the video frame based at least in part on the intermediate decoded version of the video frame and the determined amount(s) for the one or more blocks of the video frame, is disclosed. In various embodiments, the decoder may be incorporated as a part of a video system.
Type:
Grant
Filed:
October 30, 2014
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventor:
Neelesh N. Gokhale
Patent number: D737824
Type:
Grant
Filed:
August 30, 2013
Issued:
September 1, 2015
Assignee:
Intel Corporation
Inventors:
Harish Jagadish, Gokul Subramaniam, Madhukar Patil