Intel Patents
Application number: 20150333806
Abstract: A system, apparatus, method and article to manage channel prediction for a wireless communication system are described. The apparatus may include a media access control processor to perform channel prediction, and a transceiver to communicate information using the channel prediction. Other embodiments are described and claimed.
Type:
Application
Filed:
April 20, 2015
Issued:
November 19, 2015
Assignee:
INTEL CORPORATION
Inventors:
Qinghua Li, Xintian E. Lin
Application number: 20150334465
Abstract: Peer to peer (P2P) technology is utilized to allow a personal video recorder (PVR) to obtain copies of past broadcasts, Ire one configuration, electronic program guides (EPS) are used to display past, present and future broadcasts, selection of a past broadcast results in a search of a P2P network for the broadcast. If the broadcast is available, it is provided to the requester.
Type:
Application
Filed:
July 28, 2015
Issued:
November 19, 2015
Assignee:
INTEL CORPORATION
Inventors:
Carl S. Marshall, Adam T. Lake, Bradford H. Needham
Application number: 20150334152
Abstract: Technology for distributing presence information by a presence server in an Internet protocol (IP) multimedia subsystem (IMS) based dynamic adaptive streaming over hypertext transfer protocol (HTTP) (DASH) service is disclosed. In an example, a user equipment (UE) can be operable to act as a presentity and include computer circuitry configured to: Generate a trigger event during a DASH session; and publish presence information including content being consumed to a presence server. The published content can include DASH content.
Type:
Application
Filed:
December 26, 2013
Issued:
November 19, 2015
Assignee:
INTEL IP CORPORATION
Inventor:
OZGUR OYMAN
Application number: 20150333180
Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
Type:
Application
Filed:
July 23, 2015
Issued:
November 19, 2015
Assignee:
INTEL CORPORATION
Inventors:
Glenn A. Glass, Anand S. Murthy, Tahir Ghani
Application number: 20150334157
Abstract: A wireless network device to support quality-aware adaptive media streaming includes a radio-frequency transceiver, a processor operably coupled to the radio-frequency transceiver, and a memory device operably coupled to the processor. The memory storing instructions that configure the processor to parse a manifest file to read information characterizing media content available for hypertext transfer protocol (HTTP) adaptive streaming, obtain quality information of the media content based on a quality attribute parsed from the manifest file, and dynamically switch streaming between different encoded portions of the media content in response to the quality information for an encoded portion of the media content deviating from a desired quality value.
Type:
Application
Filed:
July 16, 2015
Issued:
November 19, 2015
Assignee:
Intel Corporation
Inventors:
Ozgur Oyman, Yiting Liao, Jeffrey R. Foerster
Application number: 20150333085
Abstract: A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.
Type:
Application
Filed:
July 30, 2015
Issued:
November 19, 2015
Assignee:
Intel Corporation
Inventors:
Haitao Liu, Chandra V. Mouli, Krishna K. Parat, Jie Sun, Guangyu Huang
Application number: 20150333802
Abstract: Described herein are techniques related to near field coupling and proximity sensing operations. For example, a proximity sensor uses a coil antenna that is utilized for near field communications (NFC) functions. The proximity sensor may be integrated into an NFC module to form a single module.
Type:
Application
Filed:
May 20, 2015
Issued:
November 19, 2015
Assignee:
Intel Corporation
Inventors:
SONGNAN YANG, ANAND S. KONANUR, ULUN KARACAOGLU, HAO-HAN HSU
Application number: 20150333628
Abstract: Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Described is also a voltage regulator which comprises: a signal generator to generate a pulse-width modulated (PWM) signal; a bridge having a low-side switch coupled to an output node for providing regulated voltage supply according to the PWM signal; a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage; and a bridge controller to provide control signals to the first driver. The voltage regulator may operate without diode clamps and its operation is self-timed. The voltage regulator also provides tolerance against process variation.
Type:
Application
Filed:
July 27, 2015
Issued:
November 19, 2015
Assignee:
Intel Corporation
Inventors:
Gerhard Schrom, Mark S. Milshtein, Alexander Lyakhov
Application number: 20150333478
Abstract: According to the present invention there is provided a method of operating a laser comprising the steps of; defining an intensity value (KVIDEO red, KVIDEO green, KVIDEO blue) for a light beam which is to be output from the laser; determining if the defined intensity value is greater than, or less than, a threshold intensity (KTH red, KTH green, KTH blue) for the laser, wherein the threshold intensity is the intensity of the light which is output from the laser when the input current to the laser is equal to the threshold current (ITH red, ITH green, ITH blue) of the laser, wherein the threshold current (ITH red, ITH green, ITH blue) of the laser is an input current value below which the laser would operate in its light emitting region and equal to, or above which, the laser will operate in its laser region; operating the laser using current from at least a DAC current source if the defined intensity value (KVIDEO red, KVIDEO green, KVIDEO blue) is greater than the threshold intensity (KTH red, KTH green, KTH
Type:
Application
Filed:
December 18, 2012
Issued:
November 19, 2015
Assignee:
Intel Corporation
Inventors:
NICOLAS ABELE, MOHAMMED ADHAM
Patent number: 9188446
Abstract: Aspects of the disclosure permit agile acquisition of a location service in a device. In one aspect of such acquisition, the device can rely on location signals available globally in order to determine a region associated with the device, and in response to determination of the region, the device can acquire service information representative or otherwise indicative of the location service based at least on the region. In another aspect, the device can be configured to consume the location service. The agility of such acquisition can stem from the absence of (i) scanning for location services associated with the area in which the device is present and/or (ii) a predefined pool of location services established in production of the device.
Type:
Grant
Filed:
December 28, 2013
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Gil Zukerman, Anna Miskiewicz, Ron Rotstein
Patent number: 9186909
Abstract: A system, article, and method to provide lens shading color correction using block matching.
Type:
Grant
Filed:
September 26, 2014
Issued:
November 17, 2015
Assignee:
INTEL CORPORATION
Inventor:
Dmytro Paliy
Patent number: 9188753
Abstract: Methods, apparatuses, and systems related to optical connector assemblies are described. In some embodiments, the connector assemblies may include an optical assembly, having an optical interconnect and an optical module, to be coupled with a host electrical connector. The connector assembly may further include springs, disposed on the optical interconnect or the host electrical connector, to facilitate a coupling of the optical interconnect with the optical module. Other embodiments are described and claimed.
Type:
Grant
Filed:
March 12, 2013
Issued:
November 17, 2015
Assignee:
INTEL CORPORATION
Inventors:
Simon S. Lee, Brian H. Kim, Jennie Lou H. De Quinto
Patent number: 9189073
Abstract: A transition mechanism for a computing system utilizing user sensing. An embodiment of an apparatus includes a sensing element to sense a presence or movement of a user of the apparatus, a processor, wherein operation of the processor includes interpretation of user gestures to provide input to the apparatus, and a light generation element to generate a light to indicate existence of a virtual boundary of the apparatus. The computing device is to change from a first state to a second state upon the sensing element sensing that at least a portion of the user is within the virtual boundary.
Type:
Grant
Filed:
December 23, 2011
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Rajiv Mongia, Achintya Bhowmik, Mark Yahiro, Dana Krieger, Ed Mangum, Diana Povieng
Patent number: 9189046
Abstract: In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.
Type:
Grant
Filed:
March 4, 2013
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Xiuting C. Man, Michael N. Derr, Jay D. Schwartz, Stephen H. Gunther, Jeremy J. Shrall, Shaun M. Conrad, Avinash N. Ananthakrishnan
Patent number: 9189230
Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
Type:
Grant
Filed:
March 31, 2004
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Edward T. Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James P. Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
Patent number: 9189056
Abstract: Various embodiments are generally directed to operation of a computing device powered with first and second sets of energy storage cells, the cells of the first set structurally optimized for higher density storage of electric power, and the cells of the second set structurally optimized for providing electric power at a high electric current level. A battery module includes a casing, a first cell disposed within the casing to store electric energy with a high density, and a second cell disposed within the casing to provide electric energy stored therein with a high current level. Other embodiments are described and claimed herein.
Type:
Grant
Filed:
December 26, 2012
Issued:
November 17, 2015
Assignee:
INTEL CORPORATION
Inventors:
Tawfik M. Rahal-Arabi, Alexander B. Uan-Zo-Li, Mark MacDonald, Vivek M. Paranjape, Andy Keates, Don J. Nguyen
Patent number: 9189014
Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
Type:
Grant
Filed:
October 30, 2012
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
Patent number: 9189302
Abstract: A technique to monitor events within a computer system or integrated circuit. In one embodiment, a software-accessible event monitoring storage and hardware-specific monitoring logic are selectable and their corresponding outputs may be monitored by accessing a counter to count events corresponding to each of software-accessible storage and hardware-specific monitoring logic.
Type:
Grant
Filed:
January 29, 2014
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventor:
Lance Hacking
Patent number: 9189411
Abstract: Embodiments of an invention for logging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having an associated enclave page cache address. The execution unit is to execute the instruction without causing a virtual machine exit, wherein execution of the instruction includes logging the instruction and the associated enclave page cache address.
Type:
Grant
Filed:
December 28, 2012
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Francis X. Mckeen, Michael A. Goldsmith, Barrey E. Huntley, Simon P. Johnson, Rebekah Leslie, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith
Patent number: 9189360
Abstract: A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.
Type:
Grant
Filed:
June 15, 2013
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Beeman C. Strong, Jason W. Brandt, Tsvika Kurts, Peter Lachner, Itamar Kazachinsky, Stephen J. Robinson, Peggy J. Irelan
Patent number: 9189373
Abstract: Systems and methods of conducting interoperability assessments provide for generating a feature interoperability matrix based on feature data and interoperability data, wherein the feature data defines a plurality of features of a product and the interoperability data indicates levels of interoperability of the plurality of features. A validation set can be generated based on the feature interoperability matrix, wherein the validation set includes a plurality of feature combinations. A subfeature interoperability matrix can be used to convert the validation set into a test plan for the product, wherein the test plan minimizes test configurations for the product.
Type:
Grant
Filed:
December 24, 2013
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventor:
Satwant Kaur
Patent number: 9189398
Abstract: A processor is described comprising: an architectural register file implemented as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, and a data location table (DLT) to store data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache.
Type:
Grant
Filed:
December 28, 2012
Issued:
November 17, 2015
Assignee:
INTEL CORPORATION
Inventors:
Ilan Pardo, Michael Behar, Oren Ben-Kiki, Dror Markovich
Patent number: 9189617
Abstract: An apparatus and method for zero knowledge proof security techniques within a computing platform. One embodiment includes a security module executed on a processing core to establish a domain of trust among a plurality of layers by sending a challenge from a verification layer to a first prover layer, the challenge comprising an indication of at least one selected option; in response to receiving the challenge, generating first verification information at the first prover layer based on the secret and the indication of the selected option; sending the first verification information to at least a second prover layer, the second prover layer generating second verification information based on the first verification information and the indication of the selected option; and performing a verification operation at the verification layer using the second verification information based on the selected option.
Type:
Grant
Filed:
September 27, 2013
Issued:
November 17, 2015
Assignee:
INTEL CORPORATION
Inventor:
Brent M. Sherman
Patent number: 9189426
Abstract: Embodiments of techniques and systems for protected access to virtual memory are described. In embodiments, a protected memory management architecture (“PMMA”) may be configured to control accesses to protected physical memory. The PMMA may provide a protected virtual memory window for dynamic allocation of protected memory regions. During forward translation of virtual memory addresses, the PMMA may check a region ID of a process before allowing access. During reverse translation of a physical memory address, the PMMA may prevent accesses to protected physical memory addresses. The PMMA may also dynamically allocate physical memory to protected memory regions in virtual memory and may authenticate the physical memory as available before allocation. Other embodiments may be described and claimed.
Type:
Grant
Filed:
June 28, 2012
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Chee Hak Teh, Weng Li Leow, Alok K. Mathur
Patent number: 9189439
Abstract: In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.
Type:
Grant
Filed:
December 27, 2013
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Ramana Rachakonda, Lance E. Hacking, Mahesh K. Reddy, Lori R. Borger, Chee Hak Teh, Pawitter P. Bhatia, John P. Lee
Patent number: 9189441
Abstract: Methods and apparatus for supporting dual casting of inbound system memory writes from PCIe devices to memory and a peer PCIe device. An inbound system memory write request from a first PCIe device is received at a PCIe root complex and the memory address is inspected to determine whether it falls within an address window defined for dual casting operations. If it does, an IO write request is generated from the inbound system memory write request and sent to a second PCIe device associated with the address window. During a parallel operation, the original inbound system memory write request is forwarded to a system agent configured to receive such write requests.
Type:
Grant
Filed:
October 19, 2012
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Jayakrishna Guddeti, Luke Chang
Patent number: 9189445
Abstract: A method and a device for synchronizing broadcast of streaming data by a transmitting data processing unit to a plurality of receiving data processing units is provided. After a data word has been sent, a synchronizer in the transmitting data processing unit collects an acknowledge signal from each of the receiving data processing units and then generates an indication that the next data word can be transmitted. This allows to speed-up data delivery to parallel working processing units in a system-on-a-chip since data delivery has no longer to account for a maximum predictable latency of the respective receiving units.
Type:
Grant
Filed:
February 9, 2011
Issued:
November 17, 2015
Assignee:
Intel Mobile Communications GmbH
Inventor:
Uwe Porst
Patent number: 9189233
Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.
Type:
Grant
Filed:
June 26, 2012
Issued:
November 17, 2015
Assignee:
INTEL CORPORATION
Inventors:
Ruchira Sasanka, Abhinav Das, Jeffrey J. Cook, Jayaram Bobba, Arvind Krishnaswamy, David J. Sager, Suresh Srinivas
Patent number: 9189620
Abstract: Embodiments of apparatuses, articles, methods, and systems for protecting software components using transition point wrappers are generally described herein. In one embodiment, an apparatus includes a first component, a wrapper component, and a management module. The wrapper component is to transform a transition point between the first component and a second component. The management module is to control access to the first component through the transformed transition point. Other embodiments may be described and claimed.
Type:
Grant
Filed:
June 30, 2009
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Prashant Dewan, Vedvyas Shanbhogue
Patent number: 9189945
Abstract: Systems and methods may provide for identifying an amount of time associated with a user based activity with respect to a battery powered device, and determining a battery drain rate of the battery powered device. An indicator of whether the user based activity can be completed in the amount of time may be generated based on the battery drain rate.
Type:
Grant
Filed:
November 26, 2014
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Carl S. Marshall, Selvakumar Panneer
Patent number: 9189837
Abstract: There is provided a method of processing a digital image including: (a) obtaining a plurality of images; (b) converting the plurality of images into histograms; (c) setting one of the plurality of images as a reference image and another of the plurality of images as a comparison target image; (d) adjusting a distribution of the histogram of the reference image to match a distribution of the histogram of the comparison target image to produce an adjusted reference image; (e) comparing a difference between the adjusted reference image and the comparison target image to produce a masking image; (f) applying the masking image to the comparison target image to produce an adjusted comparison target image; and (g) combining the reference image and the adjusted comparison target image to produce a high dynamic range (HDR) image. Accordingly, even if there is a complex motion on a subject, a clear image without an image overlap or a ghost effect may be obtained when producing the HDR image.
Type:
Grant
Filed:
February 15, 2013
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventor:
Minje Park
Patent number: 9189236
Abstract: According to one embodiment, a processor includes an instruction decoder to decode an instruction to read a plurality of data elements from memory, the instruction having a first operand specifying a storage location, a second operand specifying a bitmask having one or more bits, each bit corresponding to one of the data elements, and a third operand specifying a memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the instruction, to read one or more data elements speculatively, based on the bitmask specified by the second operand, from a memory location based on the memory address indicated by the third operand, and to store the one or more data elements in the storage location indicated by the first operand.
Type:
Grant
Filed:
December 21, 2012
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Jayashankar Bharadwaj, Nalini Vasudevan, Victor W. Lee, Sara S. Baghsorkhi, Albert Hartono, Daehyun Kim
Patent number: 9189237
Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
Type:
Grant
Filed:
December 27, 2012
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Yen-Kuang Chen, William W. Macy, Jr., Matthew Holliman, Eric L. Debes, Minerva M. Yeung, Huy V. Nguyen, Julien Sebot
Patent number: 9189238
Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
Type:
Grant
Filed:
January 29, 2013
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Yen-Kuang Chen, William W. Macy, Jr., Matthew Holliman, Eric L. Debes, Minerva M. Yeung, Huy V. Nguyen, Julien Sebot
Patent number: 9189240
Abstract: Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.
Type:
Grant
Filed:
November 26, 2014
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Lutz Naethke, Axel Borkowski, Bert Bretschneider, Kyriakos A. Stavrou, Rainer Theuer
Patent number: 9189246
Abstract: A processing system with multiple processing units may support separate operating systems (OSs) in separate partitions. During an initialization process, a preboot manager in the processing system may copy software to a sequestered area of memory in the processing system. The preboot manager may also configure the processing system to hide the sequestered area of memory from a first partition of the processing system. Also, the preboot manager may use a first processing unit in the processing system to boot an OS on the first partition, and the preboot manager may transmit a boot trigger from the first processing unit to a second processing unit in the processing system. The boot trigger may cause the second processing unit to use the software in the sequestered area of memory to boot a second partition of the processing system. Other embodiments are described and claimed.
Type:
Grant
Filed:
February 7, 2013
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Lyle Cool, Saul Lewites
Patent number: 9189258
Abstract: A reconfigurable sensor front-end includes a logic block having a storage circuit to store hardware description information and a reconfigurable block including a plurality of circuits. The plurality of circuits are to be set in a first configuration based on the hardware description information and are to be set in a second configuration when the hardware description information changes. The first hardware description information corresponds to a first sensor and the changed hardware description information corresponding to a second sensor.
Type:
Grant
Filed:
January 7, 2014
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventor:
Amit S. Baxi
Patent number: 9189296
Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.
Type:
Grant
Filed:
December 27, 2013
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Bahaa Fahim, Jeffrey Chamberlain, Yen-Cheng Liu
Patent number: 9190380
Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
Type:
Grant
Filed:
December 6, 2012
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Weng Hong Teh, Chia-Pin Chiu
Patent number: 9191975
Abstract: Systems and methods for transmitting location-specific information such as wireless network connectivity information are generally disclosed herein. One embodiment includes device configurations and techniques implemented to establish a secondary wireless network connection to exchange the location-specific information between a location-unaware device and a location-unaware device. In other embodiments, the location-specific information exchanged via the secondary wireless network connection includes the transfer of the connectivity information, such as a Service Set Identifier (SSID) or network authentication information, from a primary network-aware device to establish a primary network connection at a primary network-unaware device.
Type:
Grant
Filed:
September 30, 2011
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventor:
Raguraman Barathalwar
Patent number: 9190173
Abstract: A generic data scrambler is provided for a built-in self-test (BIST) engine of a stacked memory device. The stacked memory device includes a memory stack of one or more memory layers; and a system element that is coupled with the memory stack. The system element includes a memory controller for the memory stack; a BIST circuit for testing of the memory stack; and a generic data scrambler for scrambling of data according to a data scrambling algorithm for the memory stack. The generic data scrambler includes a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, and the programmable lookup table is to generate a set of data factors based on addresses of data for testing of the memory stack.
Type:
Grant
Filed:
March 30, 2012
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Darshan Kobla, David Zimmerman, John C. Johnson, Vimal K. Natarajan
Patent number: 9190388
Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes attaching an optically transparent solid material to a body of semiconducting material in which microelectronic devices are formed. The method also includes attaching a first surface of a body portion, comprising a portion of the body, to a substrate while a portion of the optically transparent solid material is attached to a second surface of the body portion. The method also includes removing the optically transparent solid material from the second surface of the body portion after the attaching the first surface of the body portion to the substrate.
Type:
Grant
Filed:
December 19, 2011
Issued:
November 17, 2015
Assignee:
INTEL CORPORATION
Inventors:
Robert L. Sankman, Edward A. Zarbock
Patent number: 9190124
Abstract: Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.
Type:
Grant
Filed:
December 29, 2011
Issued:
November 17, 2015
Assignee:
INTEL CORPORATION
Inventors:
Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick, Frank T. Hady
Patent number: 9190518
Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
Type:
Grant
Filed:
May 8, 2014
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
Patent number: 9190959
Abstract: A circuit for providing a bias signal for a power amplifier includes a first input, a second input and an output. The first input is configured to receive an input signal to be amplified by the power amplifier. The second input is configured to receive the amplified input signal. The output is configured to provide the bias signal.
Type:
Grant
Filed:
November 12, 2012
Issued:
November 17, 2015
Assignee:
Intel Deutschland GmbH
Inventors:
Andrea Camuffo, Alexander Belitzer, Bernhard Sogl
Patent number: 9190983
Abstract: A first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.
Type:
Grant
Filed:
August 22, 2012
Issued:
November 17, 2015
Assignee:
Intel Mobile Communications GmbH
Inventor:
Andreas Menkhoff
Patent number: 9190991
Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.
Type:
Grant
Filed:
December 15, 2011
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Mark Neidengard, Vaughn Grossnickle, Nasser Kurd, Jeffrey Krieger
Patent number: 9190490
Abstract: A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel.
Type:
Grant
Filed:
March 15, 2013
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Randy J. Koval, Fatma A. Simsek-Ege
Patent number: 9190700
Abstract: An improved microwave cavity filter used in cellular communication systems such as base stations is disclosed. The cavity filter has a conductive housing forming a cavity therein and a hollow conductive resonator configured in the cavity with a folded hat shaped upper portion. A tuning screw extends from the top cover of the housing into the top folded hat portion of the hollow resonator to fine tune the resonator. The resonator also may preferably include two different diameter sections providing a first high impedance section with smaller diameter and a second lower impedance section with a larger diameter configured at an upper end of the resonator. This configuration provides a significantly smaller cavity height for a given power handling capability. The resonator is preferably of constant thickness allowing low cost stamping or other forming techniques to be used in forming the resonator.
Type:
Grant
Filed:
July 31, 2014
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventor:
Purna C. Subedi
Patent number: D743334
Type:
Grant
Filed:
January 22, 2015
Issued:
November 17, 2015
Assignee:
Intel Corporation
Inventors:
Gregory A. Peek, Mark R. Francis, Torrey W. Frank, Ichiang Sun, Arthur Dietrich-Croy