Abstract: In some examples, a camera calibration method for calibrating a plurality of cameras includes determining a relationship between each camera and a unique coordinate system. The calibration method also includes determining a positional relationship between all of the plurality of cameras based on the relationships between each of the cameras and the unique coordinate system.

Abstract: Techniques related to License Assisted Access (LAA) measurement requirements are described. Briefly, in accordance with one embodiment, the requirements on the cell identification for a User Equipment (UE) is determined based at least in part on one or more Discovery Reference Signals (DRSs). Further, a cell identification period is determined based at least in part on a combination of a measurement period and a cell detection period at the UE. Other embodiments are also disclosed and claimed.

Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.

Abstract: A system and apparatus can include a printed circuit board comprising a plurality of metal layers including a first set of metal layers and a set plurality of metal layers. A conductor extending through at least the first set of metal layers and the second set of metal layers, the conductor electrically connected to a metal trace, the conductor comprising a first conducting pad, and a first segment extending from the first conducting pad to the metal trace, and a second segment extending from the metal trace in a direction away from the first conducting pad. The PCB can include a first void separating the first segment of the conductor from the first set of metal layers; and a second void separating the second segment of the conductor from the second set of metal layers, the second void larger than the first void.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a plurality of thermal parameters for a device, identify one or more of the plurality of thermal parameters that affect a thermal response of the device, and create a thermal vector for the device using the one or more of the plurality of thermal parameters that affect the thermal response of the device, where the thermal vector can be used to predict a new thermal response of the device. In an example, the thermal vector includes weighted thermal parameters.

Abstract: A monocrystalline metal-oxide stack including a ferroelectric (FE) tunneling layer and a buffer layer is epitaxially grown on a growth substrate. A first polycrystalline metal electrode layer is deposited over the tunneling layer. A bonding material layer is further deposited over the electrode layer. The bonding material layer is then bonded to a material layer on a front or back side of a host substrate that further comprises a transistor cell. Once bonded, the growth substrate may be removed from the metal-oxide stack to complete a transfer of the metal-oxide stack from the growth substrate to the host substrate. A second polycrystalline metal electrode layer is then deposited over the exposed buffer layer, placing both electrodes in close proximity to the FE tunneling layer.

Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to communicate information to a user using a first style of communication, receive language-based communication from the user, and determine that the language-based communication indicates a desire of the user to change from the first style of communication to a second style of communication.

Abstract: Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.

Abstract: There is disclosed in one example a computing apparatus, including: an active computing element; a first magnetic attractor mechanically coupled to the active computing element; and a cold plate disposed to conduct heat away from the active computing element, the cold plate including a second magnetic attractor disposed to magnetically couple with the first magnetic attractor.

Abstract: An example apparatus for detecting keywords in audio includes an audio receiver to receive audio comprising a keyword to be detected. The apparatus also includes a spike transducer to convert the audio into a plurality of spikes. The apparatus further includes a spiking neural network to receive one or more of the spikes and generate a spike corresponding to a detected keyword.

Abstract: An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

Abstract: Technology for correcting memory read errors including a preprocessing majority logic decode based on a plurality of identity structures of a parity check matrix, before ECC decoding using the parity check matrix, to estimate a set of erased or punctured bits of a codeword.

Abstract: A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.

Abstract: Embodiments of the present disclosure describe semiconductor equipment devices having a metal workpiece and a diamond-like carbon (DLC) coating disposed on a surface of the metal workpiece, thermal semiconductor test pedestals having a metal plate and a DLC coating disposed on a surface of the metal plate, techniques for fabricating thermal semiconductor test pedestals with DLC coatings, and associated configurations. A thermal semiconductor test pedestal may include a metal plate and a DLC coating disposed on a surface of the metal plate. The metal plate may include a metal block formed of a first metal and a metal coating layer formed of a second metal between the metal block and the DLC coating. An adhesion strength promoter layer may be disposed between the metal coating layer and the DLC coating. Other embodiments may be described and/or claimed.

Abstract: A method and apparatus are provided for selecting a menu item corresponding to a program to be displayed on a video display. A projector located within a sphere-shaped object projects an image of at least one menu item onto an inside surface of the sphere-shaped object, such that the image can be seen on an outer surface of the sphere-shaped object. The sphere-shaped object is rotated to cause an image of at least one other menu item to be projected onto the inside surface of the sphere-shaped object, such that the image of at least the one other menu item can be seen on an outer surface of this sphere-shaped object. The sphere-shaped object is touched to indicate that one of the displayed menu items is selected, and a video display is cause to display images associated with the selected one of the displayed menu items.

Abstract: Technologies for cryptographic protection of I/O audio data include a computing device with a cryptographic engine and an audio controller. A trusted software component may request an untrusted audio driver to establish an audio session with the audio controller that is associated with an audio codec. The trusted software component may verify that a stream identifier associated with the audio session received from the audio driver matches a stream identifier received from the codec. The trusted software may program the cryptographic engine with a DMA channel identifier associated with the codec, and the audio controller may assert the channel identifier in each DMA transaction associated with the audio session. The cryptographic engine cryptographically protects audio data associated with the audio session. The audio controller may lock the controller topology after establishing the audio session, to prevent re-routing of audio during a trusted audio session. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.

Abstract: A method for determining an image rejection characteristic of a receiver within a transceiver is provided. The transceiver uses a common local oscillator. The method includes generating a test signal having a spectral peak and generating a local oscillator signal comprising a frequency with an offset from a center frequency of the spectral peak. Further, the method includes down-mixing the test signal in the receiver using the local oscillator signal to generate a down-mixed signal. The method further includes calculating a first value of a signal characteristic of the down-mixed signal in a first frequency range corresponding to a desired signal component of the down-mixed signal and calculating a second value of the signal characteristic of the down-mixed signal in a second frequency range corresponding to an undesired signal component of the down-mixed signal. Further, the method includes comparing the first value and the second value to generate the image rejection characteristic.

Abstract: In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor to a predictor at a periodic interval and generating a prediction to indicate a predicted operation level of the cores during a next operating period. Other embodiments are described and claimed.

Abstract: Methods, apparatuses and storage medium associated with navigation service are disclosed. In various embodiments, a method may include collecting, by a client mobile device, ambient barometric pressure information at a current location of the client mobile device. The method may further include providing, by the mobile device, contemporaneous navigation assistance to a user of the mobile device or for a user of the mobile device, assisted by a remote navigation assistance service. Assistance by the remote navigation service is associated with determining the current elevation level, based at least in part on ambient barometric pressure information collected by the client mobile device and by one or more crowdsourced mobile devices at the current location. Other embodiments may be disclosed or claimed.

Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

Abstract: Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.

Abstract: A processor includes a decode unit to decode a memory copy instruction that indicates a start of a source memory operand, a start of a destination memory operand, and an initial amount of data to be copied from the source memory operand to the destination memory operand. An execution unit, in response to the memory copy instruction, is to copy a first portion of data from the source memory operand to the destination memory operand before an interruption. A descending copy direction is to be used when the source and destination memory operands overlap. In response to the interruption, when the descending copy direction is used, the execution unit is to store a remaining amount of data to be copied, but is not to indicate a different start of the source memory operand, and is not to indicate a different start of the destination memory operand.

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

Abstract: The graphics pipeline produces real time utilization data for each of a plurality of functional units making up an overall graphics processor or graphics system on a chip. This information may be used for fine grain management of power consumption and performance at the functional unit level as opposed the overall device level. As a result, the graphics functional units may be managed dynamically based on real time hardware metrics to improve performance and reduce power consumption. The technique may be implemented in a software module in one embodiment.

Abstract: Disclosed herein are integrated circuit (IC) packages with temperature sensor traces, and related systems, devices, and methods. In some embodiments, an IC package may include a package substrate and an IC die disposed on the package substrate, wherein the package substrate includes a temperature sensor trace, and an electrical resistance of the temperature sensor trace is representative of an equivalent temperature of the temperature sensor trace.

Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

Abstract: A device with support for blockchain-based boot tracking comprises at least one processor, non-volatile storage responsive to the processor, and at least one boot module in the non-volatile storage. The boot module, when executed by the processor, enables the device to generate a measurement of the boot module, generate an internal ledger transaction based on the measurement of the boot module, and send the internal ledger transaction to a remote device. In addition, the boot module enables the device to (a) receive an external ledger transaction from the remote device, wherein the external ledger transaction is based on a measurement for a boot module of the remote device; (b) in response to receiving the external ledger transaction, verify the external ledger transaction; and (c) in response to verifying the external ledger transaction, add the external ledger transaction to a boot audit blockchain. Other embodiments are described and claimed.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a speculative cache modification design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a cache communicably interfaced with the data bus; a pipeline communicably interfaced with the data bus, in which the pipeline is to receive a store instruction corresponding to a cache line to be written to cache; caching logic to perform a speculative cache write of the cache line into the cache before the store instruction retires from the pipeline; and cache line validation logic to determine if the cache line written into the cache is valid or invalid, in which the cache line validation logic is to invalidate the cache line speculatively written into the cache when determined invalid and further in which the store instruction is allowed to retire from the pipeline when the cache line is determined to be valid.

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

Abstract: An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.

Abstract: Apparatuses, methods and storage medium associated with techniques to detect soft errors of a TCAM are disclosed herein. In embodiments, an apparatus may include a TCAM, and logic and/or circuitry to apply a plurality of fault detection patterns to the TCAM to generate respective hit output arrays for the plurality of fault detection patterns, generate parity signatures for the hit output arrays, and compare the generated parity signatures to expected parity values. Other embodiments may be disclosed or claimed.

Abstract: An apparatus and method for performing search and replace operations at a storage controller of a storage device are disclosed. The storage controller can receive a search command with one or more parameters that instructs the storage controller to search for a data pattern in data stored in a memory of the apparatus. The storage controller can locally search the data in the memory for the data pattern according to the parameters without transferring the data to a processor to perform the search. The parameters can include, but are not limited to, the data pattern or template to be searched, a data pattern length, a bit-mask, a logical block address (LBA) range, a byte offset, and an alignment parameter. Verdict bits can be provided to indicate data chunks in the memory that match the data pattern. Flags may define potential outputs to provide after searching, such as location and number of matches.

Abstract: Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.

Abstract: Techniques are disclosed for processing a video stream to reduce platform power by employing a stepped and distributed pipeline process, wherein CPU-intensive processing is selectively performed. The techniques are particularly well-suited for hand-based navigational gesture processing. In one example case, for instance, the techniques are implemented in a computer system wherein initial threshold detection (image disturbance) and optionally user presence (hand image) processing components are proximate to or within the system's camera, and the camera is located in or proximate to the system's primary display. In some cases, image processing and communication of pixel information between various processing stages which lies outside a markered region is suppressed. In some embodiments, the markered region is aligned with, a mouse pad or designated desk area or a user input device such as a keyboard. Pixels evaluated by the system can be limited to a subset of the markered region.

Abstract: A processor includes a plurality of packed data registers. The processor also includes a decode unit to decode a packed variable length code point length determination instruction. The instruction is to indicate a first source packed data that is to have a plurality of packed variable length code points that are each to represent a character. The instruction is also to indicate a destination storage location. The processor also has an execution unit coupled with the decode unit and the packed data registers. The execution unit, in response to the instruction, is to store a result packed data in the indicated destination storage location. The result packed data is to have a length for each of the plurality of the packed variable length code points. Other processors, methods, systems, and instructions are also disclosed.

Abstract: Methods, apparatus, and system to analyze a memory integrity violation and determine whether its cause was hardware or software based.

Abstract: Two primitives may be merged by interpolating vertex attributes at coarse pixel centers. Input attributes are computed as a coverage weighted average of the interpolated vertex attributes. Then coarse pixel shading is performed using the merged primitives.

Abstract: Methods, software, and apparatus for implementing local service chaining (LSC) with virtual machines (VMs) or virtualized containers in Software Defined Networking (SDN). In one aspect a method is implemented on a compute platform including a plurality of VMs or containers, each including a virtual network interface controller (vNIC) communicatively coupled to a virtual switch in an SDN. LSCs are implemented via a plurality of virtual network appliances hosted by the plurality of VMs or containers. Each LCS comprises a sequence (chain) of services performed by virtual network appliances defined for the LSC. In connection with performing the chain of services, packet data is forwarded between VMs or containers using a cut-through mechanisms under which packet data is directly written to receive (Rx) buffers on the vNICs in a manner that bypasses the virtual switch. LSC indicia (e.g.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive metadata from an application, wherein the meta data indicates one or more processing operations which can accommodate a predetermined level of bit errors in read operations from memory, determine, from the metadata, pixel data for which error correction code bypass is acceptable, and generate one or more error correction code bypass hints for subsequent cache access to the pixel data for which error correction code bypass is acceptable, and transmit the one or more error correction code bypass hints to a graphics processing pipeline. Other embodiments are also disclosed and claimed.

Abstract: Image de-noising is described using an equalized gradient space. In one example, a method of de-noising an image includes determining an intensity gradient magnitude for an image, determining blurring radii for a plurality of pixels of the image using the intensity gradient, and blurring the image at each of the plurality of pixels using the blurring radii.

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract: In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.

Abstract: Technologies for multi-scale object detection include a computing device including a multi-layer convolution network and a multi-scale region proposal network (RPN). The multi-layer convolution network generates a convolution map based on an input image. The multi-scale RPN includes multiple RPN layers, each with a different receptive field size. Each RPN layer generates region proposals based on the convolution map. The computing device may include a multi-scale object classifier that includes multiple region of interest (ROI) pooling layers and multiple associated fully connected (FC) layers. Each ROI pooling layer has a different output size, and each FC layer may be trained for an object scale based on the output size of the associated ROI pooling layer. Each ROI pooling layer may generate pooled ROIs based on the region proposals and each FC layer may generate object classification vectors based on the pooled ROIs. Other embodiments are described and claimed.

Abstract: In some examples, a display includes a plurality of display backlight groups, and one or more controller to determine one or more one-dimensional backlight group brightness level adjustments, to determine one or more two-dimensional backlight group brightness level adjustments, and to adjust a brightness of one or more of the backlight groups in response to content of a display image.

Abstract: Apparatus, system and method to provide switchable coils in a computing device, comprising: a plurality of electrically conductive coils to transfer electromagnetic energy; a sensor coupled to a processor, to select a coil from among the plurality of electrically conductive coils; a switch to energize the selected coil; and a switch controller coupled to the switch and to the processor. In some embodiments, the plurality of coils may comprise an inductive charging interface. Some embodiments may further include a communication interface between the processor to the plurality of electrically conductive coils, the plurality of coils comprising an interface for near-field communications (NFC). The antenna coils may be arranged to provide improved NFC coverage when the computing device is in a respective predetermined physical configuration. Sensors may be used to detect the configuration and switch NFC communications to use a preferred antenna coil for the detected configuration.

Abstract: Methods and apparatus relating to Multi-Sample Anti-Aliasing (MSAA) memory bandwidth reduction for sparse sample per pixel utilization are described. In an embodiment, Multi-Sample Anti-Aliasing (MSAA) logic generates render subspan plane information based on data stored in a cacheline. One or more read operations to memory are suppressed based on a determination that the cacheline is in a clear state. Other embodiments are also disclosed and claimed.

Abstract: An apparatus and method for extracting and using path shading coherence in a ray tracing architecture. For example, one embodiment of a graphics processing apparatus comprises: ray generation logic to generate a ray stream from one or more image tiles; ray sorting logic to sort the rays within the ray stream based on a material identifier (ID) associated with each of the rays to generate a sorted ray stream; and one or more shaders to perform shading operations on rays within the sorted ray stream in an order in which the rays are sorted within the sorted ray stream.