Abstract: According to various examples, a vehicle controller is described comprising a determiner configured to determine information about surroundings of a vehicle, the information about the surroundings comprising information about velocities of objects in the surroundings of the vehicle and a velocity controller configured to input the information about the surroundings of the vehicle and a specification of a path of the vehicle to a convolutional neural network, to determine a target velocity of the vehicle along the path based on an output of the convolutional neural network and to control the vehicle according to the determined target velocity.

Abstract: Embodiments are generally directed to automatic adjustment of head mounted display straps. An embodiment of a head mounted display apparatus includes a display unit; a strap harness including one or more straps; one or more pressure sensors; a microcontroller; and one or more automatic adjustment mechanisms for the one or more straps, wherein the microcontroller is to adjust the one or more straps by controlling operation of the one or more automatic adjustment mechanisms based at least in part on sensor data from the one or more pressure sensors.

Abstract: A method for providing pressure feedback is described herein. The method includes receiving, via a processor, pressure sensor data from a plurality of pressure sensors over a period of time. The method also includes receiving, via the processor, movement data from a plurality of sensors over the period of time. The method also further includes sending, via the processor, pressure sensor data and movement data to a data service. The method also includes receiving, via the processor, a feedback from data service.

Abstract: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

Abstract: Methods, systems and apparatuses may provide for technology that conducts an automated vision analysis of image data associated with an interior of a vehicle cabin, determines a state of a child restraint system (CRS) based on the automated vision analysis, and generates an alert if the state of the CRS does not satisfy one or more safety constraints. In one example, the technology identifies the safety constraint(s) based on a geographic location of the vehicle cabin.

Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes a systolic dot product unit to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Abstract: Various embodiments are generally directed to providing information capture by multiple drones, which may operate in a swarm, while maintaining rights and/or value assigned to the content authored by each drone or by subsets of drones. In general, the present disclosure provides that drones participating in content acquisition may attest to their authenticity to establish trust between drones in the swarm.

Abstract: Technologies for providing predictive thermal management include a compute device. The compute device includes a compute engine and an execution assistant device to assist the compute engine in the execution of a workload.

Abstract: Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.

Abstract: Various embodiments are generally directed to techniques for multi-domain memory encryption, such as with a plurality of cryptographically isolated domains, for instance. Some embodiments are particularly directed to a multi-domain encryption system that provides one or more of memory encryption, integrity, and replay protection services to a plurality of cryptographic domains. In one embodiment, for example, an apparatus may comprise a memory and logic for an encryption engine, at least a portion of the logic implemented in circuitry coupled to the memory. In various embodiments, the logic may receive a memory operation request associated with a data line of a set of data lines stored in a protected memory separate from the memory.

Abstract: The present disclosure is directed to systems and methods of improving the efficiency and reducing the power consumption of organic light emitting diode (OLED) display devices. The OLED display device includes an OLED display layer that includes a substrate, an anode layer, a transparent cathode layer, and a plurality of OLED display pixels disposed between the anode and the cathode layers. A light-scattering layer is selectively or randomly disposed on, across, or about at least a portion of the surface of the OLED display layer. The light-scattering layer includes one or more monolayers, each of which includes a plurality of nanoparticles having a principal dimension that is greater than 10% of the wavelength of the electromagnetic energy emitted by the OLED display layer.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to de determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.

Abstract: A computing platform, including: an execution unit to execute a program, the program including a first phase and a second phase; and a quick response module (QRM) to: receive a program phase signature for the first phase; store the program phase signature in a pattern match action (PMA) table; identify entry of the program into the first phase via the PMA; and apply an optimization to the computing platform.

Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

Abstract: Systems, apparatuses and methods may provide for establishing a hardware-based chain of trust in a computing system and extending the hardware-based chain of trust to a container manager and a containerized application on the computing system. Additionally, the containerized application may be checked for its trust and security while it is launched, via the container manager, on the computing system. In one example, extending the hardware-based chain of trust includes conducting a pre-boot measurement of the container manager, a root of trust measurement agent, and one or more packages associated with the containerized application, and verifying the pre-boot measurement of the platform/host and the application itself prior to the containerized application being launched.

Abstract: Described are mechanisms and methods for amortizing the cost of address decode, row-decode and wordline firing across multiple read accesses (instead of just on one read access). Some or all memory locations that share a wordline (WL) may be read, by walking through column multiplexor addresses (instead of just reading out one column multiplexor address per WL fire or memory access). The mechanisms and methods disclosed herein may advantageously enable N distinct memory words to be read out if the array uses an N-to-1 column multiplexor. Since memories such as embedded DRAMs (eDRAMs) may undergo a destructive read, for a given WL fire, a design may be disposed to sense N distinct memory words and restore them in order.

Abstract: Various systems and methods for obtaining vendor information using mobile internet devices are described herein. An inquiry for a product or service is received from a user. A location for the receipt of the product or service is received. Vendor information of a vendor of the product or service proximate to the location is determined, with the vendor information including a price for the product or service, and a wait time to receive the product or service. The vendor information is then transmitted to the user.

Abstract: Methods, apparatuses, and computer readable media for location measurement reporting in a wireless network are disclosed. An apparatus of a responder station is disclosed, the apparatus comprising processing circuitry configured to derive bits from a temporary key, and generate a first sequence and a second sequence using the bits, wherein the first sequence and second sequence comprise one or more symbols. The processing circuitry is further configured to concatenate the first sequence and the second sequence to form a new first sequence comprising the first sequence and the second sequence, and concatenate a modified first sequence and a modified second sequence to form a new second sequence. The processing circuitry may be configured to repeat a number of times the concatenate the first sequence through the concatenate the modified first sequence.

Abstract: Identifying a local coordinate system is described for gesture recognition. In one example, a method includes receiving a gesture from a user across a horizontal axis at a depth camera, determining a horizontal vector for the user based on the received user gesture, determining a vertical vector; and determining a rotation matrix to convert positions of user gestures received by the camera to a frame of reference of the user.

Abstract: Techniques are disclosed for co-integrating thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices and III-N semiconductor transistor devices. In accordance with some embodiments, a given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (AlN), and any one, or combination, of other III-N semiconductor materials. For instance, aluminum indium nitride (AlxIn1-xN), aluminum gallium nitride (AlxGa1-xN), or aluminum indium gallium nitride (AlxInyGa1-x-yN) may be interleaved with the AlN, and the particular compositional ratios thereof may be adjusted to customize resonator performance. In accordance with some embodiments, the superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over film thicknesses, in some cases in the range of a few nanometers.

Abstract: Techniques are provided for training and operation of a topic-guided image captioning system. A methodology implementing the techniques according to an embodiment includes generating image feature vectors, for an image to be captioned, based on application of a convolutional neural network (CNN) to the image. The method further includes generating the caption based on application of a recurrent neural network (RNN) to the image feature vectors. The RNN is configured as a long short-term memory (LSTM) RNN. The method further includes training the LSTM RNN with training images and associated training captions. The training is based on a combination of: feature vectors of the training image; feature vectors of the associated training caption; and a multimodal compact bilinear (MCB) pooling of the training caption feature vectors and an estimated topic of the training image. The estimated topic is generated by an application of the CNN to the training image.

Abstract: Various systems and methods for managing graphics subsystems are described herein. A system for managing graphics subsystems of a compute device includes a display controller operable to: receive an indication that a first display of the compute device has been activated; enable a power management feature in a display controller, the power management feature to reduce power consumption of the display controller and associated components, and the power management feature to reduce graphics memory bandwidth usage; receive an indication that a second display has been activated with the first display; and maintain the power management feature for at least the first display.

Abstract: Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.

Abstract: A communication device can include a receiver frontend and a wake-up receiver (WUR) frontend. The receiver frontend can have a radio frequency (RF) interface configured to couple to an antenna and a baseband interface configured to couple to a baseband component. The WUR frontend can be selectively coupled to the receiver frontend (e.g. between the RF interface and the baseband interface). The WUR frontend may monitor a communication channel and control the receiver frontend to adjust its operating mode (e.g. waking the receiver frontend from a sleep mode) based on the monitoring. The WUR frontend may have a lower power consumption than the receiver frontend. The WUR frontend and the receiver frontend may share the same impedance matching network and/or the RF interface.

Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.

Abstract: Embodiments of fast steering timing and resource allocation are generally described herein. In some embodiments, a non-access point station (STA) decodes a fast steering timing signaling element (STSE) at a Narrow Band Control sub-Channel (NB-C-CH) and from an allocator device, the STSE indicating at least fast steering timing information, an identified Narrow Band Service sub-Channel (NB-S-CH), resource allocation information for the identified NB-S-CH, and connectivity information for the identified NB-S-CH, the identified NB-S-CH being selected from a plurality of NB-S-CHs. The STA exchanges packets in the NB-S-CH according to the resource allocation information and the connectivity information and based on the fast steering timing information. The STA encodes or decodes data associated with the exchanged packets.

Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

Abstract: Technologies for link capability estimation are disclosed. A compute device may determine a maximum radio bitrate for a certain connection, such as an LTE connection to a specific cell antenna. The compute device may also determine a maximum downlink bitrate for that connection, and store both the maximum radio bitrate and the maximum downlink bitrate in a database on the compute device. At a later time, an application of the compute device may want to know an estimate of the current maximum downlink bitrate, such as for the purpose of selecting a bitrate in streaming a video. The compute device can determine the current maximum radio bitrate, and look for similar entries in the database. Based on entries in the database, a link capability estimation can be determined and provided to the application.

Abstract: A lens antenna system is disclosed. The lens antenna system comprises a hybrid focal source antenna circuit configured to generate a source antenna beam for integration with different lens structures. In some embodiments, the hybrid focal source antenna circuit comprises a set of antenna elements coupled to one another. In some embodiments, the set of antenna elements comprises a first antenna element configured to be excited in a first spherical mode; and a second antenna element configured to be excited in a second, different, spherical mode. In some embodiments, the first spherical mode and the second spherical mode are co-polarized. In some embodiments, the lens antenna system further comprises a lens configured to shape the source antenna beam associated with the hybrid focal source antenna circuit, in order to provide an output antenna beam.

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: Technology for a wideband coverage enhancement (WCE) user equipment (UE) and a next generation node B (gNB) operable for communication in a MulteFire cell is disclosed. The WCE UE can identify selected resource blocks containing an enhanced physical downlink control channel (ePDCCH), wherein the selected resource blocks are identified using a master information block (MIB). The WCE UE can decode an ePDCCH transmission from the gNB. The WCE UE can identify a system information block MulteFire (SIB-MF) scheduled via the ePDCCH to allow the SIB-MF to be decoded.

Abstract: A variable delay circuit includes first pull-up and first pull-down current paths and second pull-up and second pull-down current paths. The variable delay circuit generates first delays in an output signal relative to an input signal in response to the first pull-up and first pull-down current paths being enabled by a first control signal. The variable delay circuit generates second delays in the output signal relative to the input signal that are different than the first delays in response to the second pull-up and second pull-down current paths being enabled by a second control signal.

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

Abstract: An apparatus of a transmitter may include, for example, a Golay builder to build modulated Golay sequences for at least a non-EDMG Short Training Field (L-STF), and a non-EDMG Channel Estimation Field (L-CEF) of a PPDU; a scrambler to generate scrambled bits by scrambling bits of a non-EDMG header (L-header) and a data field of the PPDU; an encoder to encode the scrambled bits into encoded bits according to a low-density parity-check (LDDC) code; a constellation mapper to map the encoded bits into a stream of constellation points according to a constellation scheme; a spreader to spread the stream of constellation points according to a Golay sequence; and a transmit chain mapper to map a bit stream output from the Golay builder and the spreader to a plurality of transmit chains by applying a spatial expansion with relative cyclic shift over the plurality of transmit chains.

Abstract: A Cloud federator may be used to allow seamless and transparent access by a Cloud Client to Cloud services. Federation may be provided on various terms, including as a subscription based real-time online service to Cloud Clients. The Cloud federator may automatically and transparently effect communication between the Cloud Client and Clouds and desired services of the Clouds, and automatically perform identity federation. A Service Abstraction Layer (SAL) may be implemented to simplify Client communication, and Clouds/Cloud services may elect to support the SAL to facilitate federation of their services.

Abstract: Techniques are provided for optimizing the operations of an ICN, particularly for an ICN with clustered nodes. A cluster head node may function as an orchestrator and a coordinator for efficient caching, routing, and computing and for co-existence of ICN and IP nodes in the network. A content store of an ICN router may include an indication of the time after which data expires and the new data is to be swapped in place of the expired data after that point in time. Digital rights management (DRM) enforcement is provided by managing access to a DRM engine in at least one of the ICN nodes in a cluster. Congestion control is provided by minimizing the number of ICN scoped interest requests and thereby minimizing the potentially high volume of data responses. These techniques optimize interest packet forwarding and processing through collaboration with neighboring ICN nodes.

Abstract: Methods and apparatus to adaptively manage data collection devices in distributed computing systems are disclosed. Example disclosed methods involve instructing a first data collection device to operate according to a first rule. The example first rule specifies a first operating mode and defining a first event of interest. Example disclosed methods also involve obtaining first data from the first data collection device while operating according to the first rule. Example disclosed methods also involve, in response to determining that the first event of interest has occurred based on the first data, providing a second rule based on the first data to the first data collection device, and providing a third rule to a second data collection device. The example second rule specifies a second operating mode and defines a second event of interest, and the examples third rule specifies a third operating mode.

Abstract: A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.

Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

Abstract: An example apparatus for encoding video frames includes a receiver to receive a current frame to be encoded, and a quantization parameter and statistics for the current frame. The apparatus also includes a frame motion analyzer to detect a motion activity status for the current frame based on the statistics via a motion activity analysis. The apparatus further includes a motion adaptive frame inserter to adaptively switch between a regular reference list management and a long-term reference frame insertion based on the detected motion activity status and the quantization parameter. The apparatus also further includes an encoder to encode the current frame using the regular reference list management or the long-term reference frame insertion.

Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.

Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to identify sub-operations of a collective operation of a collective operation request received from one of the computing nodes and identify a plurality of operands for each of the sub-operations. The network switch is additionally configured to request a value for each of the operands from a corresponding target computing node at which the respective value is stored, determine a result of the collective operation as a function of the requested operand values, and transmit the result to the requesting computing node. Other embodiments are described herein.

Abstract: Technologies for providing certified telemetry data indicative of resource utilizations include a device with circuitry configured to obtain telemetry data indicative of a utilization of one or more device resources over a time period. The circuitry is additionally configured to sign the obtained telemetry data with a private key associated with the present device. Further, the circuitry is configured to send the signed telemetry data to a telemetry service for analysis.

Abstract: In one embodiment, a portable computing device is described. The portable computing device includes a first surface comprising at least one user interface. The portable computing device also includes a second surface opposite the first surface. Further, the portable computing device includes at least one speaker port in the first surface. Further yet, the portable computing device includes a collapsible speaker chamber configured on the second surface opposite the at least one speaker port. Moreover, the portable computing device includes a speaker configured in the portable computing device between the speaker port and the collapsible speaker chamber.

Abstract: Two liquid cooling mechanisms are provided for cooling integrated circuit components immersed in an open bath immersion tank. In the first mechanism, heat generated by high-thermal design power (TDP) components is absorbed by a working fluid passing through cold plates coupled to the high-TDP components. The cold plates are part of direct liquid cooling loops attached to supply and return manifolds fluidly connected to a cooling distribution unit. In the second mechanism, integrated circuit components not coupled to any of the direct liquid cooling loops dissipate heat directly to the immersion fluid. In some embodiments, the tank is a closed bath immersion tank and heat captured by the working fluid is reclaimed and converted to electricity. Working fluid flow rate can be adjusted based on integrated circuit component power consumption levels to achieve a desired working fluid temperature as it enters an energy reclamation unit.

Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.

Abstract: An apparatus to facilitate matrix processing is disclosed. The apparatus comprises a matrix accelerator to receive input matrix data, transform the input matrix data into a plurality of sub-blocks, examine a first block of the sub-blocks to determine whether the first block comprises sparse data, select a first tile size upon a determination that the first block comprises sparse data and generate output matrix data based on the first tile size.

Abstract: In one embodiment, an apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link.