Abstract: For example, a wireless communication device may be configured to, in a passive scan of a plurality of wireless communication channels, perform an energy detection over the plurality of wireless communication channels during an energy detection period, the energy detection configured to identify for a wireless communication channel of the plurality of wireless communication channels whether or not energy is detected over the wireless communication channel; and based on detection of energy over a first wireless communication channel of the plurality of wireless communication channels during the energy detection period, perform a wireless packet detection over the first wireless communication channel to detect a wireless packet transmission, the wireless packet detection to be performed while continuing the energy detection over one or more second wireless communication channels of the plurality of wireless communication channels to detect energy over the one or more second wireless communication channels.

Abstract: A method for coordinating communication amongst a plurality of mobile devices, includes generating joint transmission information describing transmission information for use by the plurality of mobile devices in transmitting data related to a cooperative communication message to a destination node and instructing a mobile device to transmit a coordination message to the plurality of mobile devices, wherein the coordination message includes the joint transmission information.

Abstract: Apparatus, methods, and systems for tuple space search-based flow classification using cuckoo hash tables and unmasked packet headers are described herein. A device can communicate with one or more hardware switches. The device can include memory to store hash table entries of a hash table. The device can include processing circuitry to perform a hash lookup in the hash table. The lookup can be based on an unmasked key include in a packet header corresponding to a received data packet. The processing circuitry can retrieve an index pointing to a sub-table, the sub-table including a set of rules for handling the data packet. Other embodiments are also described.

Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region 308 within the conductive structure. Other embodiments are described and claimed.

Abstract: An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

Abstract: In one example a system for emotional adaptive driving policies for automated driving vehicles, comprising a first plurality of sensors to detect environmental information relating to at least one passenger in a vehicle and a controller communicatively coupled to the plurality of sensors and comprising processing circuitry, to receive the environmental information from the first plurality of sensors, determine, from the environmental information, an emotional state of the at least one passenger, and implement a driving policy based at least in part on the emotional state of the at least one passenger. Other examples may be described.

Abstract: A system for unmanned aerial vehicle alignment including: an image sensor, configured to obtain an image of unmanned aerial vehicles and provide to a processor image data corresponding to the obtained image, the processor, configured to determine from the image data image positions of the unmanned aerial vehicles, determine an average position of the unmanned aerial vehicles relative to a first axis based on the image positions, determine an average line that extends along a second axis through the average position, wherein the first and second axes are perpendicular to each other, determine a target position of one of the unmanned aerial vehicles based on a relationship between its respective image position and a target alignment, and determine an adjustment instruction to direct said one of the unmanned aerial vehicles toward the target position, and provide the adjustment instruction to said one of the unmanned aerial vehicles.

Abstract: Technologies for managing data object requests in a storage node cluster include a proxy computing node communicatively coupled to the cluster of storage nodes. The proxy computing node is configured to receive data object requests from a communicatively coupled client computing device and identify a plurality of storage nodes of the cluster at which the data object of the data object request is stored. The proxy computing node is further configured to determine which of the identified storage nodes from which to retrieve the stored data object and transmit a request for the data object. Additionally, the proxy computing node is configured to estimate a request completion time based on a service time and a wait time for each of the identified storage nodes, as well as identify which of the storage nodes to retrieve the stored data object from based on the estimated request completion times. Other embodiments are described and claimed.

Abstract: Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.

Abstract: Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.

Abstract: A system is provided that includes an instruction buffer that stores bytes representative of one or more macroinstructions and instruction length decoder circuitry. The instruction length decoder circuitry includes a non-sequential first multiplexer circuitry having first input lines receiving a first input data representative of a speculative length of a first macroinstruction of the macroinstructions, and first selector that selects from the first input lines via a one-hot selector vector. The instruction length decoder circuitry also includes a first output line communicatively coupled to second selector, wherein the first output line causes the selector to select from a second input data representative of a first location of a first ending byte for the first macroinstruction with respect to a value x. The first multiplexer circuitry and the second selector may output start and end byte locations for the macroinstructions.

Abstract: One embodiment includes hardware logic to: receive first and second communications corresponding to an intellectual property (IP) core and begin a timed session in response to receiving the second communication; determine the firmware has completed processing the second communication before expiration of the timed session and increase a latency state corresponding to a resource in response to determining the firmware has completed processing the second communication before expiration of the timed session; receive a third communication corresponding to the IP core and begin an additional timed session in response to receiving the third communication; determine the firmware failed to complete processing the third communication before expiration of the additional timed session and decrease the latency state corresponding to the resource in response to determining the firmware failed to complete processing the third communication before expiration of the additional timed session.

Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.

Abstract: A systolic array implemented in circuitry of an integrated circuit, includes a processing element array having processing elements arranged in a vertical direction and a horizontal direction, first loaders communicatively coupled to the processing element array to load samples Am,n from at least one external memory to the processing element array, and second loaders communicatively coupled to the processing element array to load samples Bk,l from the at least one external memory to the processing element array. Each row of the samples Am,n is loaded one row at a time to a single processing element along the horizontal direction, and each row of the samples Bk,l is loaded one row at a time to a single processing element along the vertical direction, wherein pairing between the samples Am,n and Bk,l in the horizontal direction and the vertical direction enables data reuse to reduce bandwidth usage of the external memory.

Abstract: Embodiments described include methods, apparatuses, and systems including a permutation generator to permute locations of one or more bits (e.g., data bits and/or parity bits) in a codeword. In embodiments, the bits are to be written to a memory device based on the permuted locations to reduce a recurrence of bit error patterns associated with the bits when stored in the memory device. In some embodiments, the locations are based at least in part on a pseudorandom number, generated based at least in part on information available at a read time and a write time. In some embodiments, the pseudorandom number is based upon a memory address of the memory device, such as a 3D NAND or other memory device.

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

Abstract: Herein is disclosed an infrastructure state prediction device comprising a memory device onto which an infrastructure state model corresponding to a location and a state timing of a plurality of infrastructure elements is stored; one or more processors, communicatively coupled to the memory device and configured to receive measurement information representing a location and an observed state of a first infrastructure element; determine a predicted state of a second infrastructure element based on a state timing corresponding to a second infrastructure element; determine a movement information based on the observed state of the first infrastructure element, the predicted state of the second infrastructure element and a relation between the location of the first infrastructure element and a location of the second infrastructure element; and generate a message comprising the movement information.

Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.

Abstract: A device, a system, and a method. The device is configured to be part of a first wireless apparatus, and comprises a memory, and processing circuitry coupled to the memory and including logic to cause the first wireless apparatus to: perform a WUR Mode setup frame exchange with a Primary Connectivity Radio (PCR) of a second wireless apparatus; establish a Wake-Up Radio (WUR) Mode operation with the second wireless apparatus based on the frame exchange; transmit a Wake-Up Radio (WUR) Teardown Frame to the PCR of the second wireless apparatus, the WUR Mode Teardown frame including information to cause a teardown of the WUR Mode operation with the second wireless apparatus; and process an acknowledgment message (ACK) from the second wireless apparatus to tear down the WUR Mode operation with the second wireless apparatus.

Abstract: An embodiment of a graphics processor pipeline apparatus may include a vertex fetcher to fetch vertices, a vertex shader communicatively coupled to the vertex fetcher to shade the fetched vertices, a primitive assembler communicatively coupled to the vertex shader to assemble primitives, and a primitive replicator communicatively coupled to the primitive assembler to replicate primitives for at least a first and a second viewport.

Abstract: Systems, methods, and apparatuses relating to debugging a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. At least a first of the plurality of processing elements is to enter a halted state in response to being represented as a first of the plurality of dataflow operators.

Abstract: Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit as a device under test (DUT). During hardware emulation operations, an emulation host may be used to coordinate testing of the DUT on the programmable device. In particular, the programmable device may include configurable memory elements such as lookup-table random-access memory (LUTRAM) elements that are operable in a LUT mode and a memory mode. An emulation controller may be used to dynamically assert a global emulation request signal, which forces each LUTRAM element that belong to the DUT in the LUT mode, thereby allowing the emulation host to readily access their internal states without having to perform partial reconfiguration.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to develop driving simulations. An example apparatus includes a vehicle configuration engine to retrieve first tier environment parameters associated with a simulation type, and generate second tier environment parameters associated with the simulation type, a simulation modifier (SM) source engine to identify a source of SMs, and distinguish respective ones of the source of SMs that are compatible with the simulation type and the second tier environment parameters, and a development environment configuration engine to improve simulation design efficiency by associating simulation events with only the respective ones of the SMs that are compatible with the simulation type.

Abstract: A high current fast read scheme can enable improved read disturb without negatively impacting read performance. In one example, a fast read scheme involves applying a higher current as soon as the cell thresholds. In one example, circuitry detects the threshold event and turns on a bypass control transistor to bypass the circuitry applying the read voltage to enable a higher voltage and therefore higher current as soon as possible. The read time can thus be decreased (or at least not increased) and read disturb improved.

Abstract: Methods and apparatuses for vehicles, including unmanned aerial vehicles (UAV). A method for traffic control can include detecting a traffic condition; determining whether to adjust a virtual traffic sign responsive to detecting the traffic condition; and adjusting the virtual traffic sign based on the traffic condition. Adjusting the virtual traffic sign can include encoding a message for transmission to a base station within a range of the virtual traffic sign, the message including at least one of a virtual traffic sign type and a virtual traffic sign value. Other methods, systems, and apparatuses are described.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

Abstract: Apparatus and method for asynchronous ray tracing.

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density 3D SRAM. An example device includes an SRAM cell built based on a first nanoribbon, suitable for forming NMOS transistors, and a second nanoribbon, suitable for forming PMOS transistors. Both nanoribbons may extend substantially in the same plane above a support structure over which the memory device is provided. The SRAM cell includes transistors M1-M4, arranged to form two inverter structures. The first inverter structure includes transistor M1 in the first nanoribbon and transistor M2 in the second nanoribbon, while the second inverter structure includes transistor M3 in the first nanoribbon and transistor M4 in the second nanoribbon. The IC device may include multiple layers of nanoribbons, with one or more such SRAM cells in each layer, stacked upon one another above the support structure, thus realizing 3D SRAM.

Abstract: A communication circuitry device for correcting a phase imbalance, the communication circuitry device comprising one or more processors configured to estimate a non-linear component of a reference signal based on a measurement of a tone at a first harmonic of a plurality of harmonics of the reference signal, estimate an in-phase component of the reference signal based on subtracting the non-linear component from a measurement of a tone at a second harmonic of the plurality of harmonics of the reference signal, and generate a calibration signal based on the estimation of the in-phase component.

Abstract: In one example, a nonvolatile memory device, such as a NAND flash memory device, includes an array of non-volatile memory cells. Program operations performed by the memory may be suspended (e.g., in order to service a high priority read request). The memory device includes a timer to track a duration of time the program operation is suspended. Upon program resume, the controller applies a program voltage after resume that is adjusted based on the duration of time the program operation is suspended.

Abstract: A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.

Abstract: In one example a computer implemented method comprises encrypting data to be stored in a protected region of a memory using a message authentication code (MAC) having a first value determined using a first key during a first period of time, generating a replay integrity tree structure comprising security metadata for the data stored in the protected region of the memory using the first value of the MAC, and at the end of the first period of time, re-keying the MAC to have a second value determined using a second key at the end of the first period of time, decrypting the data stored in the protected region using the first value for the MAC, re-encrypting the data stored in the protected region using the second value for the MAC, and updating the replay integrity tree using the second value for the MAC. Other examples may be described.

Abstract: A memory device includes a first electrode, a non-volatile memory element having a first terminal and a second terminal, where the first terminal is coupled to the first electrode. The memory device further includes a selector having a first terminal, a second terminal and a sidewall between the first and second terminals, where the second terminal of the selector is coupled to the first terminal of the non-volatile memory element. A second electrode is coupled to the second terminal of the selector and a third electrode laterally adjacent to the sidewall of the selector.

Abstract: Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.

Abstract: An embedded dynamic random-access memory cell includes a wordline to supply a gate signal, a selector thin-film transistor (TFT) above the wordline and that includes an active layer and is configured to control transfer of a memory state of the memory cell between a first region and a second region of the active layer in response to the gate signal, a bitline to transfer the memory state and coupled to and above the first region of the active layer, a storage node coupled to and above the second region of the active layer, and a metal-insulator-metal capacitor coupled to and above the storage node and configured to store the memory state. In an embodiment, the wordline is formed in a back end of line process for interconnecting logic devices formed in a front end of line process below the wordline, and the selector TFT is formed in a thin-film process.

Abstract: Systems, methods, and computer-readable media are disclosed for an apparatus coupled to a communication bus, where the apparatus includes a queue and a controller to manage operations of the queue. The queue includes a first space to store a first information for a first traffic type, with a first flow class, and for a first virtual channel of communication between a first communicating entity and a second communicating entity. The queue further includes a second space to store a second information for a second traffic type, with a second flow class, and for a second virtual channel of communication between a third communicating entity and a fourth communicating entity. The first traffic type is different from the second traffic type, the first flow class is different from the second flow class, or the first virtual channel is different from the second virtual channel. Other embodiments may be described and/or claimed.

Abstract: Data is received describing a local model of a first device generated by the first device based on sensor readings at the first device and a global model is updated that is hosted remote from the first device based on the local model and modeling devices in a plurality of different asset taxonomies. A particular operating state affecting one or more of a set of devices deployed in a particular machine-to-machine network is detected and the particular machine-to-machine network is automatically reconfigured based on the global model.

Abstract: A mechanism is described for facilitating system characterization and configuration distribution for promoting improved performance at computing devices. A method of embodiments, as described herein, includes selecting a computing device from a plurality of computing devices to perform a test relating to a default configuration corresponding to the computing device, where the computing device is selected based on at least one of a workload being initiated at the computing device or overall performance of the computing device. The method may further include evaluating feedback data resulting from the test to decide whether a change is necessitated for the default configuration, and computing a new configuration to replace the default configuration at the computing device, if the change is necessitated for the default configuration.

Abstract: Technologies disclosed herein provide one example of a processor that includes a register to store a first encoded pointer for a first memory allocation for an application and circuitry coupled to memory. Size metadata is stored in first bits of the first encoded pointer and first memory address data associated with the first memory allocation is stored in second bits of the first encoded pointer. The circuitry is configured to determine a first memory address of a first marker region in the first memory allocation, obtain current data from the first marker region at the first memory address, compare the current data to a reference marker stored separately from the first memory allocation, and determine that the first memory allocation is in a first state in response to a determination that the current data corresponds to the reference marker.

Abstract: In one embodiment, an apparatus includes a port to transmit and receive data over a link; and protocol stack circuitry to implement one or more layers of a load-store input/output (I/O)-based protocol (e.g., PCIe or CXL) across the link. The protocol stack circuitry constructs memory write request transaction layer packets (TLPs) for memory write transactions, wherein fields of the memory write request TLPs indicate a virtual channel (VC) other than VCO, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction. The memory write request TLP is transmitted over the link and a completion TLP is received over the link in response, indicating a completion for the memory write request TLP.

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

Abstract: The application provides a method, comprising: generating identifying information at an access point (AP), the identifying information including information relating to an energy detection (ED) threshold to be used for a channel in a wireless network; and broadcasting the identifying information via the channel.

Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line.

Abstract: Techniques for liquid cooling systems are disclosed. In one embodiment, jet holes in a water block create jets of liquid coolant to be applied to a surface to be cooled, such as a surface of an integrated circuit component. The jets of liquid coolant may disrupt surface boundary layers through turbulence and/or microcavitation, increasing the cooling effect of the liquid coolant. In the illustrative embodiment, negative pressure is applied to a coolant loop of the liquid coolant, which provides several advantages such as being resistant to leaks. In another embodiments, jet holes in a water block create jets of liquid coolant that are directed toward other jets of liquid coolant, which also increases the cooling effect of the liquid coolant.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.

Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store visual data associated with a visual representation captured by one or more sensors. The processor is to: obtain the visual data associated with the visual representation captured by the one or more sensors, wherein the visual data comprises uncompressed visual data or compressed visual data; process the visual data using a convolutional neural network (CNN), wherein the CNN comprises a plurality of layers, wherein the plurality of layers comprises a plurality of filters, and wherein the plurality of filters comprises one or more pixel-domain filters to perform processing associated with uncompressed data and one or more compressed-domain filters to perform processing associated with compressed data; and classify the visual data based on an output of the CNN.