Patents by Inventor David A. Hardell

Abstract: Methods and apparatus for mitigating the effects of interference between multiple air interfaces located on an electronic device. In one embodiment, the air interfaces include a WLAN interface and PAN (e.g., Bluetooth) interface, and information such as Receiver Signal Strength Index (RSSI) as well as system noise level information are used in order to intelligently execute interference mitigation methodologies, including the selective application of modified frequency selection, variation of transmitter power, and/or change of operating mode (e.g., from multiple-in multiple-out (MIMO) to single-in, single-out (SISO)) so as to reduce isolation requirements between the interfaces. These methods and apparatus are particularly well suited to use cases where the WLAN interface is operating with high data transmission rates. Business methods associated with the foregoing technology are also described.

Abstract: A system to eliminate acoustic noise caused by a first MLCC (Multi-Layer Ceramic Capacitor) array positioned on a PCB (printed circuit board) is disclosed. The first MLCC array generates a first vibration responsible for the acoustic noise in response to receiving a varying input voltage. A third MLCC array senses the first vibration and generates a feedback signal. An adaptive filter then uses the feedback signal to generate an output signal that is used by a second MLCC to generate a second vibration that acts as a counter to dampen the first vibration. Because the input voltage signal is varying in time, the adaptive filter continually samples the varying input voltage and the feedback signal to generate the output signal that minimizes the acoustic noise. The second and third MLCC arrays are selectively positioned and oriented on the PCB for optimum performance.

Abstract: Methods and apparatus for mitigating the effects of interference between multiple air interfaces located on an electronic device. In one embodiment, the air interfaces include a WLAN interface and PAN (e.g., Bluetooth) interface, and information such as Receiver Signal Strength Index (RSSI) as well as system noise level information are used in order to intelligently execute interference mitigation methodologies, including the selective application of modified frequency selection, variation of transmitter power, and/or change of operating mode (e.g., from multiple-in multiple-out (MIMO) to single-in, single-out (SISO)) so as to reduce isolation requirements between the interfaces. These methods and apparatus are particularly well suited to use cases where the WLAN interface is operating with high data transmission rates. Business methods associated with the foregoing technology are also described.

Abstract: Methods and apparatus for mitigating the effects of interference between multiple air interfaces located on an electronic device. In one embodiment, the air interfaces include a WLAN interface and PAN (e.g., Bluetooth) interface, and information such as Receiver Signal Strength Index (RSSI) as well as system noise level information are used in order to intelligently execute interference mitigation methodologies, including the selective application of modified frequency selection, variation of transmitter power, and/or change of operating mode (e.g., from multiple-in multiple-out (MIMO) to single-in, single-out (SISO)) so as to reduce isolation requirements between the interfaces. These methods and apparatus are particularly well suited to use cases where the WLAN interface is operating with high data transmission rates. Business methods associated with the foregoing technology are also described.

Abstract: A card connector that allows a card to be at least partially coplanar with a logic board is described herein. A system having a card at least partially coplanar with a logic board is also disclosed. A card connector that allows at least one longitudinal plane through the logic board to intersect at least a point of the card is also disclosed. The card may be a memory module.

Abstract: A chip package for a computer system includes a substrate having a first region and a second region on a first surface, at least one die coupled to the first region on the first surface of the substrate and a main logic board coupled to the second region on the first surface of the substrate. By coupling the die and the main logic board on the first surface of the substrate, an overall thickness of the chip package is reduced.

Abstract: A card connector that allows a card to be at least partially coplanar with a logic board is described herein. A system having a card at least partially coplanar with a logic board is also disclosed. A card connector that allows at least one longitudinal plane through the logic board to intersect at least a point of the card is also disclosed. The card may be a memory module.

Abstract: A card connector that allows a card to be at least partially coplanar with a logic board is described herein. A system having a card at least partially coplanar with a logic board is also disclosed. A card connector that allows at least one longitudinal plane through the logic board to intersect at least a point of the card is also disclosed. The card may be a memory module.

Abstract: A chip package for a computer system includes a substrate having a first region and a second region on a first surface, at least one die coupled to the first region on the first surface of the substrate and a main logic board coupled to the second region on the first surface of the substrate. By coupling the die and the main logic board on the first surface of the substrate, an overall thickness of the chip package is reduced.

Abstract: A card connector that allows a card to be at least partially coplanar with a logic board is described herein. A system having a card at least partially coplanar with a logic board is also disclosed. A card connector that allows at least one longitudinal plane through the logic board to intersect at least a point of the card is also disclosed. The card may be a memory module.