Patents Examined by Philip Guyton
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Patent number: 10970186Abstract: Techniques are described for modeling variations in correlation to facilitate analytic operations. In one or more embodiments, at least one computing device receives first metric data that tracks a first metric for a first target resource and second metric data that tracks a second metric for a second target resource. In response to receiving the first metric data and the second metric data, the at least one computing device generates a time-series of correlation values that tracks correlation between the first metric and the second metric over time. Based at least in part on the time-series of correlation data, an expected correlation is determined and compared to an observed correlation. If the observed correlation falls outside of a threshold range or otherwise does not satisfy the expected correlation, then an alert and/or other output may be generated.Type: GrantFiled: December 7, 2018Date of Patent: April 6, 2021Assignee: Oracle International CorporationInventors: Sampanna Salunke, Dustin Garvey, Uri Shaft, Lik Wong
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Patent number: 10963329Abstract: A checking module is coupled to one or more registers to verify data written to the one or more registers. The checking module includes a memory coupled to an arbiter to receive data and an address (corresponding to the data) from the arbiter. The data is written to the one or more registers at the address. Comparator logic is coupled to the memory and to the one or more registers to compare the data written to the one or more registers and the data in the memory. An error flag circuit is coupled to the comparator logic, and in response to a difference between the data in the memory and the data written to the one or more registers, the error flag circuit outputs an error signal.Type: GrantFiled: October 17, 2018Date of Patent: March 30, 2021Assignee: OmniVision Technologies, Inc.Inventor: Dapeng Han
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Patent number: 10942798Abstract: In one example of the technology, via a first independent execution environment of a set of independent execution environments in an integrated circuit, a first watchdog timer is caused to reset on a periodic basis. The set of independent execution environments is configured to have a defense-in-depth hierarchy. The set of independent execution environments includes a first independent execution environment and a second independent execution environment. The first independent execution environment is a most trusted execution environment on the integrated circuit. Via the second independent execution environment: a second watchdog timer is periodically caused to reset on a periodic basis. In response to the second watchdog timer timing out, an interrupt is communicated from the second watchdog timer to the first independent execution environment. In response to the first watchdog timer timing out, at least a portion of the integrated circuit is reset.Type: GrantFiled: May 31, 2018Date of Patent: March 9, 2021Assignee: Microsoft Technology Licensing, LLCInventors: George Thomas Letey, Douglas L. Stiles, Edmund B. Nightingale, Stephen E. Hodges, Philip John Joseph Wright
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Patent number: 10936400Abstract: Methods and systems for dynamic handling of call home data are provided. A system for providing dynamic handling of call home data includes an event detection module that detects one or more events in the operation of one or more components. The system may also include a data request module that requests call home instructions from an upload data manager in response to the detected one or more events. Also, the upload data manager provides call home instructions. The system may further include a call home transmission module that collects call home data based on the call home instructions and provides the collected data to an upload server.Type: GrantFiled: December 4, 2018Date of Patent: March 2, 2021Assignee: International Business Machines CorporationInventors: Christof Schmitt, Erik Rueger
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Patent number: 10936412Abstract: According to some embodiments, a backup storage system receives a request from a client to access a data segment. The system looks up an in-memory index for a first entry based on a fingerprint of the data segment, such that the in-memory index includes a number of entries, each entry mapping a fingerprint to a storage location of a solid state device (SSD) storing a corresponding data segment. In the event a first entry is found, the system retrieves the data segment from the SSD device based on the first entry. In the event of a read failure while accessing the SSD device, the system determines failed data blocks of the SSD device associated with the failure event and invalidates the failed data blocks of the SSD device such that subsequent access to the failed data blocks are denied without having to access a corresponding SSD device.Type: GrantFiled: April 17, 2017Date of Patent: March 2, 2021Assignee: EMC IP HOLDING COMPANY LLCInventors: Satish Visvanathan, Rahul B. Ugale
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Patent number: 10929229Abstract: A computer-implemented method, according to one embodiment, includes: receiving a write request at a storage system which includes more than one storage device, determining a storage location for data included in the write request, and determining a storage location for parity information corresponding to the data included in the write request. A first copy of the data included in the write request is sent to a first storage device which corresponds to the storage location for the data included in the write request. Moreover, a second copy of the data included in the write request is sent to a second storage device which corresponds to the storage location for the parity information. One or more instructions to compute the parity information via a decentralized communication link with the remaining storage devices are sent to the second storage device. The first storage device is different than the second storage device.Type: GrantFiled: June 21, 2018Date of Patent: February 23, 2021Assignee: International Business Machines CorporationInventors: Radu I. Stoica, Roman A. Pletka, Ioannis Koltsidas, Nikolas Ioannou, Antonios K. Kourtis, Sasa Tomic, Charalampos Pozidis, Brent W. Yardley
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Patent number: 10922180Abstract: A technique for handling uncorrected memory errors (UEs) inside a kernel text section, the kernel text section being stored in a memory that is operably coupled to a CPU executing kernel program instructions. In an embodiment, a UE is detected that affects the kernel text section. The current instruction affected by the UE is identified. The UE-affected instruction is recovered by loading a copy thereof into the memory from a kernel image maintained in persistent storage. The UE-affected instruction is emulated using the copy of the UE-affected instruction. The instruction pointer of the CPU is then incremented to point to a next instruction in the memory that would normally be executed by the UE-affected instruction had there been no UE.Type: GrantFiled: October 3, 2018Date of Patent: February 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mahesh J. Salgaonkar, Anshuman Khandual, Srikar Dronamraju, Haren Myneni
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Patent number: 10915481Abstract: An approach is provided in which an information handling system detects a reduced capacity on a PCIe link that interfaces a host system to a PCIe I/O expansion drawer over a first/second physical cable. The information handling system verifies a first/second connection to a first/second connector on the PCIe I/O expansion drawer, receives a first/second set of vital product data over the first/second physical cable, and determines that the first physical cable and the second physical cable are connected to the same PCIe I/O expansion drawer based on analyzing the first/second set of vital product data. The information handling system then suspends operation of one or more components corresponding to the PCIe link and trains the PCIe link to an increased capacity. In turn, the information handling system resumes operation of the one or more components and restores the PCIe link to the increased capacity.Type: GrantFiled: April 18, 2019Date of Patent: February 9, 2021Assignee: International Business Machines CorporationInventors: Curtis S. Eide, Christopher J. Engel, Aditya Saripalli
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Patent number: 10896083Abstract: Systems, apparatus and methods for intelligent deployment(s) of application objects are provided. The systems, apparatus and methods may include one or more dynamic parameters retrieved from metadata table(s). The parameter(s) may be used to calibrate the deployment(s). The parameter(s) may be associated with previous failed deployment(s). Calibration may be automatic. Calibration may include email sending and/or email previewing components. A testing environment may be used prior to actual deployment.Type: GrantFiled: September 6, 2019Date of Patent: January 19, 2021Assignee: Bank of America CorporationInventors: Kiran Kumar Ampabathina, Balamurali Lakshminarayanan, Kalyan Chakravarty Saraswatula, Rahul Devane, Srinath Nelakuditi
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Patent number: 10891203Abstract: A method for creating a common platform graphical user interface is provided. The interface may enable a user to trigger a data load job from a tool. The tool may monitor file upload events, trigger jobs and identify lists of missing or problematic file names. The tool may run on a single thread, thereby consuming relatively less system resources than a multi-thread program to perform its capabilities. The tool may enable selection of file names using wildcard variables or keyword variables. The tool may validate a list of files received against a master file list for each data load job. The tool may receive user input relating to each data load job. The tool may generate a loop within the single thread to receive information. The tool may analyze the received information and use the received information to predict future metadata associated with future data load jobs.Type: GrantFiled: August 20, 2019Date of Patent: January 12, 2021Assignee: Bank of America CorporationInventors: Sireesh Kumar Vasantha, Suki Ramasamy
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Patent number: 10884843Abstract: In a system having at least two data storage and processing sites, each capable of alternatively serving as a primary site and a backup or target site, disaster recovery migration is optimized by cognitively analyzing at least one system parameter. Using machine learning, at least one pattern of that system related parameter is predicted, and planned or unplanned migration procedures are performed based on the predicted parameter patterns. The analyzed parameter may be data traffic at the sites, and the predicted data traffic pattern is used to assign primary and backup site status to those sites. The analyzed parameter may be the occurrence of events or transactions at the sites, and the predicted event or transaction patterns may be used to determine times of disaster recovery procedure processing so as to not interrupt a critical event or transaction.Type: GrantFiled: January 12, 2018Date of Patent: January 5, 2021Assignee: International Business Machines CorporationInventors: Jes Kiran Chittigala, Santhosh Joshi, Srirama R. Kucherlapati
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Patent number: 10884850Abstract: A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.Type: GrantFiled: July 24, 2018Date of Patent: January 5, 2021Assignee: Arm LimitedInventors: Reiley Jeyapaul, Roxana Rusitoru, Jonathan Curtis Beard
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Patent number: 10866862Abstract: Embodiments of the present application provide operation retry methods and apparatuses. One exemplary method includes: detecting whether an operation of a job fails; if there is an operation failure, collecting statistics on a progress of the job; calculating a retry interval according to the progress of the job; and re-executing the operation after waiting for the retry interval. When an operation of a job fails, the retry interval can be adaptively calculated according to the progress of the job. This can help increase the length of the retry interval, especially for a long job. The job can thereby be retried dynamically, to cope with longer service interruption. Embodiments of the present application can help avoid waste of resource waste caused by job failure and job re-execution, and reduce the retry costs while ensuring the success rate of the job.Type: GrantFiled: March 16, 2018Date of Patent: December 15, 2020Assignee: ALIBABA GROUP HOLDING LIMITEDInventor: Qiang Li
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Patent number: 10860515Abstract: Herein is disclosed an integrated input/output (“I/O”) processing system, comprising an I/O port, configured to receive I/O data and to deliver the I/O data to one or more processors; one or more processors, further comprising a first processing logic and a second processing logic, wherein the one or more processors are configured to deliver the received I/O data to the first processing logic and to the second processing logic, and wherein the first processing logic and the second processing logic are configured to redundantly process the I/O data; and a comparator, configured to compare an output of the first processing logic and an output of the second processing logic.Type: GrantFiled: June 21, 2018Date of Patent: December 8, 2020Assignee: INTEL CORPORATIONInventors: Swadesh Choudhary, Bahaa Fahim, Mahesh Wagh
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Patent number: 10860453Abstract: An index anomaly detection method includes: acquiring data of each of monitoring points, contained in a period of time, of a monitored index; extracting a mean value and a variance of the data of the monitoring points using a Gaussian model; calculating, according to the mean value and the variance of the data of the monitoring points, probabilities of occurrence of the data of the monitoring points, respectively; calculating, according to the respectively calculated probabilities, joint probabilities of occurrence of the data of the monitoring points contained in respective windows divided from the period of time; and detecting, according to the joint probabilities corresponding to the respective windows, whether the monitored index is abnormal.Type: GrantFiled: January 22, 2020Date of Patent: December 8, 2020Assignee: Advanced New Technologies Co., Ltd.Inventor: Longfei Li
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Patent number: 10852984Abstract: One or more techniques and/or systems are provided for mirror vote synchronization. For example, a first storage device is located at a first storage site, and a second storage device is located at a second storage site. The second storage device is configured according to a data mirroring configuration where data from the first storage device is mirrored to the second storage device. Mirror vote metadata is generated based upon an up-to-date state of the data mirroring configuration. The mirror vote metadata indicates whether the first storage device and/or the second storage device are up-to-date or not. The mirror vote metadata may be replicated between the first storage site and the second storage site. If the first storage site fails, then the second storage site may provide switchover operation using the second storage device based upon the mirror vote metadata.Type: GrantFiled: January 4, 2019Date of Patent: December 1, 2020Assignee: NetApp Inc.Inventors: Brandon Taylor Long, Linda Ann Riedle, Manali Kulkarni, Sandeep T. Nirmale, Vikram Harakere Krishnamurthy
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Patent number: 10848263Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a TX (transmission) data rate adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.Type: GrantFiled: June 20, 2018Date of Patent: November 24, 2020Assignee: SILICON MOTION, INC.Inventor: Fu-Jen Shih
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Patent number: 10838790Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.Type: GrantFiled: December 28, 2018Date of Patent: November 17, 2020Assignee: Intel CorporationInventor: Thanunathan Rangarajan
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Patent number: 10838834Abstract: A system and method for efficiently distributing data among multiple storage devices. A data storage array receives read and write requests from multiple client computers. The data storage array includes multiple storage devices, each with multiple allocation units (AUs). A storage controller within the data storage array determines a RAID layout for use in storing data. In response to determining a failure of a first AU, the storage controller begins reconstructing in a second AU the data stored in the first AU. For read and write requests targeting data in the first AU, the request is serviced by the first AU responsive to determining no error occurs when accessing the first AU.Type: GrantFiled: February 19, 2019Date of Patent: November 17, 2020Assignee: Pure Storage, Inc.Inventors: Marco Sanvido, Richard Hankins, Naveen Neelakantam, Xiaohui Wang, Mark McAuliffe, Taher Vohra
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Patent number: 10838800Abstract: A tuple testing and routing operator in a streaming application routes data tuples to multiple parallel test operators that test in parallel the data tuples, receives feedback from the multiple parallel test operators regarding the results of testing the data tuples, routes a data tuple to a first operator when the data tuple passes the multiple parallel test operators according to a specified pass threshold, and optionally routes the data tuple to a second operator when the data tuple does not pass the multiple parallel test operators according to the specified pass threshold. The pass threshold allows testing to be done in a way that does not require all tests to be performed for all data tuples, thereby enhancing performance.Type: GrantFiled: February 27, 2019Date of Patent: November 17, 2020Assignee: International Business Machines CorporationInventors: Eric L. Barsness, Michael J. Branson, Alexander Cook, John M. Santosuosso