Abstract: A non-contact power charging, in which power transmission can be interrupted when foreign materials are deposited on a charge plate of the non-contact power charging system. A charging operation can be continuously maintained at a stable voltage even if a non-contact power receiving apparatus moves by touching or displacement on the charge plate of the non-contact power charging system in the charging operation. Charging efficiency is improved.

Abstract: Technologies for protocol execution include a command device to broadcast a protocol message to a plurality of computing devices and receive an aggregated status message from an aggregation system. The aggregated status message identifies a success or failure of execution of instructions corresponding with the protocol message by the plurality of computing devices such that each computing device of the plurality of computing devices that failed is uniquely identified and the success of remaining computing devices is aggregated into a single success identifier.

Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.

Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

Abstract: A system comprising a traffic handler comprising circuitry to determine that data of a memory request is stored remotely in a memory pool; generate a packet based on the memory request; and direct the packet to a path providing a guaranteed latency for completion of the memory request.

Abstract: A system comprising a network-on-chip (NOC) fabric comprising a plurality of routes to communicate data between a plurality of agents; a plurality of built-in self-test (BIST) generators, wherein a BIST generator of the plurality of BIST generators is coupled between an agent of the plurality of agents and the NOC fabric and is to transmit at least one test pattern through the NOC fabric; and a plurality of BIST checkers, wherein a BIST checker of the plurality of BIST checkers is coupled between the agent of the plurality of agents and the NOC fabric and is to receive at least one test pattern through the NOC fabric from at least one of the plurality of BIST generators and to verify whether the at least one test pattern was transmitted correctly through the NOC fabric.

Abstract: Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed.

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Abstract: Magnetic structures may be incorporated into integrated circuit assemblies, which will enable local heating and reflow of solder interconnects for the attachment of integrated circuit devices to electronic substrates. Such magnetic structures will eliminate exposure of the entire integrated circuit assembly to elevated temperatures for an extended period of time, which eliminates associated warpage and thermal degradation consequences from such exposure. Additionally, such magnetic structures will allow for re-workability of specific solder interconnects.

Abstract: A single-substrate electroless (EL) plating apparatus including a workpiece chuck that is rotatable about rotation axis and inclinable about an axis of inclination. The chuck inclination may be controlled to a non-zero inclination angle during a dispense of plating solution to improve uniformity in the surface wetting and/or plating solution residence time across the a surface of a workpiece supported by the chuck. The angle of inclination may be only a few degrees off-level with the plating solution dispensed from a nozzle that scans over a high-side of the chuck along a radius of the workpiece while the chuck rotates. The angle of inclination may be actively controlled during dispense of the plating solution. The inclination angle may be larger at commencement of the plating solution dispense than at cessation of the dispense.

Abstract: A hybrid thermal interface material (TIM) suitable for an integrated circuit (IC) die package assembly. The hybrid TIM may include a heat-spreading material having a high planar thermal conductivity, and a supplemental material having a high perpendicular thermal conductivity at least partially filling through-holes within the heat-spreading material. The hybrid TIM may offer a reduced effective spreading and vertical thermal resistance. The heat-spreading material may have high compressibility (low bulk modulus or low hardness), such as a carbon-based (e.g., graphitic) material. The supplemental material may be of a suitable composition for filling the through-hole. The heat-spreading material, once compressed by a force applied through an IC die package assembly, may have a thickness substantially the same as that of the supplemental material such that both materials make contact with the IC die package and a thermal solution.

Abstract: A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

Abstract: Implementations describe a computing system that implements a plurality of virtual machines inside a trust domain (TD), enabled via a secure arbitration mode (SEAM) of the processor. A processor includes one or more registers to store a SEAM range of memory, a TD key identifier of a TD private encryption key. The processor is capable of initializing a trust domain resource manager (TDRM) to manage the TD, and a virtual machine monitor within the TD to manage the plurality of virtual machines therein. The processor is further capable of exclusively associating a plurality of memory pages with the TD, wherein the plurality of memory pages associated with the TD is encrypted with a TD private encryption key inaccessible to the TDRM. The processor is further capable of using the SEAM range of memory, inaccessible to the TDRM, to provide isolation between the TDRM and the plurality of virtual machines.

Abstract: Techniques and mechanisms for power management of display devices based on an indication that a user exhibits interest in one, but not all, of said display devices. In an embodiment, logic of a computer device identifies a condition wherein a user of the computer device exhibits insufficient interest in a first display device, while exhibiting at least some interest user in a second display device. The first display device and the second display device support an extended display mode of an operating system. Based on the condition, the logic automatically reduces a consumption of power by the first display device. Of the first display device and the second display device, only the first display device is subjected to a power state transition based on the condition.

Abstract: One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the ternary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.

Abstract: A write request causes controller circuitry to write an encrypted data line and First Tier metadata portion including MAC data and a first portion of ECC data to a first memory circuitry portion and a second portion of ECC data to a sequestered, second memory circuitry portion. A read request causes the controller circuitry to read the encrypted data line and the First Tier metadata portion from the first memory circuitry portion. Using the first portion of the ECC data included in the First Tier metadata portion, the controller circuitry determines if an error exists in the encrypted data line. If no error is detected, the controller circuitry decrypts and verifies the data line using the MAC data included in the First Tier metadata portion. If an error in the data line is detected by the controller circuitry, the Second Tier metadata portion, containing the second portion of the ECC data is fetched from the sequestered, second memory circuitry portion and the error corrected.

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

Abstract: The present invention discloses a secure ML pipeline to improve the robustness of ML models against poisoning attacks and utilizing data provenance as a tool. Two components are added to the ML pipeline, a data quality pre-processor, which filters out untrusted training data based on provenance derived features and an audit post-processor, which localizes the malicious source based on training dataset analysis using data provenance.

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

Abstract: A mechanism is described for facilitating training and deploying of pose regression in neural networks in autonomous machines. A method, as described herein, includes facilitating capturing, by an image capturing device of a computing device, one or more images of one or more objects, where the one or more images include one or more training images associated with a neural network. The method may further include continuously estimating, in real-time, a present orientation of the computing device, where estimating includes continuously detecting a real-time view field as viewed by the image capturing device and based on the one or more images. The method may further include applying pose regression relating to the image capturing device using the real-time view field.

Abstract: Implementations of the disclosure provide a processing device comprising an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.

Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the second side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.

Abstract: An apparatus to facilitate machine learning matrix processing is disclosed. The apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters and a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.

Abstract: An apparatus is described including cryptography circuitry to generate authentication tags to provide integrity protection for plaintext and ciphertext.

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

Abstract: Techniques for increasing link efficiency are disclosed. In one embodiment, a device handle table is created at each end of a link. Device handle allocation messages can be used to associate a particular device handle with a particular domain identifier, such as a bus/device/function (BDF) identifier or a processor address space identifier (PASID). Once a device handle is allocated, messages can be sent between the two ends of the link that include the device handle. The device handle can be used to determine the domain identifier associated with the message. As the device handle can be fewer bits than the domain identifier, the link efficiency can be increased.

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

Abstract: Techniques, structures, and materials related to extreme ultraviolet (EUV) lithography are discussed. Multiple patterning inclusive of first patterning a grating of parallel lines and second patterning utilizing EUV lithography to form plugs in the grating, and optional trimming of the plugs may be employed. EUV resists, surface treatments, resist additives, and optional processing inclusive of plug healing, angled etch processing, electric field enhanced post exposure bake are described, which provide improved processing reliability, feature definition, and critical dimensions.

Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device according to some embodiments of the present disclosure includes a first nanoribbon of a first semiconductor material, and a second nanoribbon of a second semiconductor material, where the second nanoribbon is stacked above the first, thus forming a 3D structure. The device further includes a first transistor having a first source or drain (S/D) region and a second S/D region in the first nanoribbon, and a second transistor having a first S/D region and a second S/D region in the second nanoribbon. The first transistor may be configured to store a memory state of the memory cell, and the second transistor may be configured to control access to the memory cell, thus, together forming a nanoribbon-based 2T memory cell.

Abstract: Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

Abstract: In one embodiment, an apparatus includes first and second via structures in a substrate. Each via structure defines a coupling element that extends from the via structure toward the other via structure such that the coupling elements capacitively couple with one another in an area between the first and second via structures.

Abstract: A system includes at least one processor and at least one non-transitory computer-readable media communicatively coupled to the at least one processor. In some embodiments, the at least one non-transitory computer-readable media stores instructions which, when executed, cause the processor to perform operations including receiving a first set of sensor data within a first time frame and receiving a set of skycam actions within the first time frame. In certain embodiments, the operations also include generating a set of reference actions corresponding to the first set of sensor data and the set of skycam actions. In some embodiments, the operations also include receiving a second set of sensor data associated with a second game status, a second game measurement, or both. The operations also include generating a sequence of skycam actions based on a comparison between the second set of sensor data and the set of reference actions.

Abstract: In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes: a plurality of execution lanes to perform parallel execution of instructions; and a unified symbolic store address buffer coupled to the plurality of execution lanes, the unified symbolic store address buffer comprising a plurality of entries each to store a symbolic store address for a store instruction to be executed by at least some of the plurality of execution lanes. Other embodiments are described and claimed.

Abstract: Methods, apparatus, systems and articles of manufacture for detecting a side channel attack using hardware performance counters are disclosed. An example apparatus includes a hardware performance counter data organizer to collect a first value of a hardware performance counter at a first time and a second value of the hardware performance counter at a second time. A machine learning model processor is to apply a machine learning model to predict a third value corresponding to the second time. An error vector generator is to generate an error vector representing a difference between the second value and the third value. An error vector analyzer is to determine a probability of the error vector indicating an anomaly. An anomaly detection orchestrator is to, in response to the probability satisfying a threshold, cause the performance of a responsive action to mitigate the side channel anomaly.

Abstract: Apparatuses and methods relating to an enhanced serial peripheral interface (eSPI) port expander circuitry are described. In an embodiment, an apparatus includes an upstream eSPI port, a plurality of downstream eSPI ports, and an eSPI aggregator. The upstream eSPI port is to operate as an eSPI slave on an upstream eSPI bus. Each of the plurality of downstream eSPI ports is to operate as an eSPI master on a corresponding one of a plurality of downstream eSPI buses. The eSPI aggregator is to forward or broadcast transactions from the upstream eSPI bus to one or more of the plurality of downstream eSPI buses and to aggregate responses from one or more of the downstream eSPI buses.

Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; circuitry to traverse one or more of the rays through the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes, wherein the circuitry is to process entries from the top of a first data structure comprising entries each associated with a child node at the current BVH level, the entries being ordered from top to bottom based on a sorted distance of each respective child node.

Abstract: A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.

Abstract: An embodiment of an image processor device includes technology to fetch a feature point data set from outside a local memory, locally store three or more fetched feature point data sets in the local memory, compute orientation information for each fetched feature point data set, compute first descriptor information based on the computed orientation information and a first locally stored feature point data set in parallel with a fetch and local store of a second feature point data set in the local memory, and compute second descriptor information based on the computed orientation information and the second locally stored feature point data set in parallel with the compute of the first descriptor information. Other embodiments are disclosed and claimed.

Abstract: A convolutional neural network framework is described that uses reverse connection and obviousness priors for object detection. A method includes performing a plurality of layers of convolutions and reverse connections on a received image to generate a plurality of feature maps, determining an objectness confidence for candidate bounding boxes based on outputs of an objectness prior, determining a joint loss function for each candidate bounding box by combining an objectness loss, a bounding box regression loss and a classification loss, calculating network gradients over positive boxes and negative boxes, updating network parameters within candidate bounding boxes using the joint loss function, repeating performing the convolutions through to updating network parameters until the training converges, and outputting network parameters for object detection based on the training images.

Abstract: An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.

Abstract: Frequency modulated lasers, LIDAR systems, and methods of controlling laser are disclosed. A laser source emits an optical beam having an optical frequency that changes in response to a signal applied to an input of the laser source. A laser driver that generates the signal applied to the input to cause the optical frequency to vary in accordance with a periodic frequency versus time function. The laser driver generates the signal for a current period of the periodic frequency versus time function based, at least in part, on optical frequency versus time measurements of one or more prior periods of the periodic frequency versus time function.

Abstract: An integrated circuit may include a memory controller circuit for communicating with an off-chip memory device. The memory controller is operable in a read-write major mode that is capable of dynamically adapting to any memory traffic pattern, which results in improved memory scheduling efficiency across different user applications. The memory controller may include at least a write command queue, a read command queue, an arbiter, and a command scheduler. The command scheduler may monitor a write command count, a read command count, a write stall count, and a read stall count to determine whether to dynamically adjust a read burst threshold setting and a write burst threshold setting.

Abstract: Technologies for synchronizing triggered operations include a host fabric interface (HFI) of a compute device configured to receive an operation execution command associated with a triggered operation that has been fired and determine whether the operation execution command includes an instruction to update a table entry of a table managed by the HFI. Additionally, the HFI is configured to issue, in response to a determination that the operation execution command includes the instruction to update the table entry, a triggered list enable (TLE) operation and a triggered list disable (TLD) operation to a table manager of the HFI and disable a corresponding table entry in response to the TLD operation having been triggered, the identified table entry. The HFI is further configured to execute one or more command operations associated with the received operation execution command and re-enable, in response to the TLE operation having been triggered, the table entry. Other embodiments are described herein.

Abstract: Technologies for generating 3D and using models are described. In some embodiments the technologies employ a content creation device to produce a 3D model of an environment based at least in part on depth data and color data, which may be provided by one or more cameras. Contextual information such as location information, orientation information, etc., may also be collected or otherwise determined, and associated with points of the 3D model. Access points to the imaged environments may be identified and labeled as anchor points within the 3D model. Multiple 3D models may then be combined into an aggregate model, wherein anchor points of constituent 3D models in the aggregate model are substantially aligned. Devices, systems, and computer readable media utilizing such technologies are also described.

Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.

Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.

Abstract: Mouth guard that includes a flexible printed circuit board encapsulated within a base member is provided. The flexible printed circuit board includes multiple separate stiff sections spaced apart from each other within the base member. One or more electronic devices are disposed within the base member. In particular, the one or more electronics are disposed on the base member.