Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type
  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Virtual carrier sensing with two network allocation vectors
    Patent number: 11234269
    Abstract: Methods, computer readable media, and wireless apparatuses are disclosed for virtual carrier sensing with two network allocation vectors (NAV). An apparatus of a wireless device is disclosed. The apparatus comprising processing circuitry configured to: determine a duration of a frame, determine whether the frame is an intra basic service set (Intra-BSS) frame, an inter-BSS frame, or an unclassified frame. The processing circuitry may be further configured to set an intra-BSS network allocation vector (NAV) to the duration of the frame, if the frame is determined to be the intra-BSS frame, and if a receiver address is decoded from the frame and the receiver address is not an address of the wireless device. The processing circuitry may be further configured to set a regular NAV to the duration of the frame, if the frame is determined to be the inter BSS frame or the unclassified frame.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Po-Kai Huang, Qinghua Li, Robert J. Stacey
  • Discovery reference signal and control resource set multiplexing
    Patent number: 11234219
    Abstract: Embodiments of the present disclosure describe methods and apparatuses for multiplexing control information of discovery reference signals.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Bishwarup Mondal, Prerana Rane, Yongjun Kwak, Debdeep Chatterjee
  • Network component, system and method
    Patent number: 11234254
    Abstract: According to various aspects, a network component may include: one or more processors configured to: generate a first message to a wireless network client, the first message including a request to report information about wireless networks within communication range of the wireless network client; assign a scheduling group of a plurality of scheduling groups to the wireless network client based on the information; schedule one or more transmissions in accordance with a first wireless network protocol to the wireless network client in accordance with the schedule group assigned to the wireless network client; generate a second message to the wireless network client, the second message including an instruction to schedule one or more transmissions in accordance with a second wireless network protocol from the wireless network client in accordance with the schedule group assigned to the wireless network client.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: January 25, 2022
    Assignee: INTEL CORPORATION
    Inventors: Ofer Hareuveni, Rony Ross, Daniel Bravo, Ehud Reshef, Laurent Cariou
  • Server selection for vehicle communications and applications
    Patent number: 11234204
    Abstract: Systems, apparatuses, methods, and computer-readable media, are provided for selecting edge or central servers for serving client systems based on network events monitored by one or more network elements. Embodiments may be relevant to multi-access edge computing (MEC) and Automotive Edge Computing Consorium (AECC) technologies. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Zongrui Ding, Qian Li, Xiaopeng Tong, Leifeng Ruan
  • Technologies for providing dynamic persistence of data in edge computing
    Patent number: 11232127
    Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ramanathan Sethuraman, Timothy Verrall, Ned Smith
  • Structural optimization of contact geometry for high performance connector
    Patent number: 11233348
    Abstract: A connector includes a connector housing forming a receptacle configured to receive an add-in card. The connector further includes a first connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The first connector pin extends from the connector housing to contact a first solder pad disposed on a printed circuit board (PCB). The connector further includes a second connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The second connector pin extends from the connector housing to contact a second solder pad disposed on the PCB. The first connector pin is oriented toward the second connector pin to couple to the PCB in a toe-routing configuration and the second connector pin is oriented away from the first connector pin to couple to the PCB in the toe-routing configuration.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Se-Jung Moon, Chien-Ping Kao, Gaudencio Hernandez Sosa, Beom-Taek Lee
  • Zero latency BSS transition with on-channel tunneling (OCT)
    Patent number: 11234174
    Abstract: Embodiments of transitioning between BSSs using on-channel tunneling (OCT) are generally described herein. OCT procedures are used for scanning and association with a co-located or non-co-located peer AP. The OCT procedures include communicating a Probe/Re-authentication/Re-association Request frame from a STA using an OCT Request frame to the peer AP and receiving a Probe/Re-authentication/Re-association Response frame from the peer AP using another OCT Request frame. The communications between the STA and the AP are either in the same frequency band or a different frequency band as the OCT communications between the AP and the peer AP.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Laurent Cariou, Carlos Cordeiro, Daniel F. Bravo, Ehud Reshef
  • Technologies for data center multi-zone cabling
    Patent number: 11233712
    Abstract: Technologies for connecting data cables in a data center are disclosed. In the illustrative embodiment, racks of the data center are grouped into different zones based on the distance from the racks in a given zone to a network switch. All of the racks in a given zone are connected to the network switch using data cables of the same length. In some embodiments, certain physical resources such as storage may be placed in racks that are in zones closer to the network switch and therefore use shorter data cables with lower latency. An orchestrator server may, in some embodiments, schedule workloads or create virtual servers based on the different zones and corresponding latency of different physical resources.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Michael T. Crocker
  • Haptic gloves for virtual reality systems and methods of controlling the same
    Patent number: 11231781
    Abstract: Example haptic gloves for virtual reality systems and related methods are disclosed herein. An example apparatus disclosed herein includes a glove to be worn on a hand of a user, an ultrasonic array disposed on an inner surface of the glove, and a control unit to activate the ultrasonic array device to generate haptic feedback on the hand of the user.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Yuan Xiong, Feiyue Zhai, Buddy Cao, Wenlong Yang
  • System, apparatus and method for sensor-driven and heuristic-based minimum energy point tracking in a processor
    Patent number: 11231731
    Abstract: In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Sriram R. Vangal, Jayanth Mallanayakanahalli Devaraju, Vivek De, Robert Milstrey, Stephen H. Gunther
  • Apparatus and method for assigning velocities to write data
    Patent number: 11231873
    Abstract: An apparatus is described. The apparatus includes velocity assignment logic to assign a velocity to data that is to be written to a non volatile storage medium. The velocity assignment logic is to accept input information pertaining to an identity of an application that is writing the data, the data type of the data and the state of the application in order to determine the velocity.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventor: Sanjeev N. Trika
  • Thermal dissipation in dual-chassis devices
    Patent number: 11231757
    Abstract: There is disclosed a computing apparatus, including: a first chassis including primary operational circuitry of the computing apparatus; a second chassis hingeably coupled to the second chassis, the second chassis having substantially less operational circuitry than the first chassis whereby the operational circuitry of the second chassis generates substantially less heat than the operational circuitry of the first chassis; and a heat spreader between the first chassis and second chassis and disposed to dissipate generated heat from the first chassis into the second chassis.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Prakash Kurma Raju, Babu Triplicane Gopikrishnan, Bijendra Singh, Prasanna Pichumani, Raghavendra Doddi, Harish Jagadish, Gopinath Kandasamy, David Pidwerbecki
  • Enabling sync header suppression latency optimization in the presence of retimers for serial interconnect
    Patent number: 11232058
    Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
  • Content adaptive display power savings systems and methods
    Patent number: 11231762
    Abstract: The present disclosure is directed to systems and methods for reducing display image power consumption while maintaining a consistent, objectively measurable, level of image distortion that comports with a display image quality metric. Raw image data is converted to an HSV format. “V” values are extracted from the HSV format raw image data and a histogram generates a plurality of “V” values. HSV format raw image data is provided to at least one layer of a trained CNN to extract a plurality of features. The plurality of “V” values and the plurality of features are provided to an AI circuit to generate a plurality of distortion class value pairs. Each of the distortion class value pairs is weighted based on proximity of display image distortion and the display image quality metric. The distortion class pair providing a display image distortion close to the display image quality metric is applied to the raw image data to generate the display image data.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Shravan Kumar Belagal Math, Tamoghna Ghosh, Sherine Abdelhak, Junhai Qiu
  • Power monitoring for a processing platform
    Patent number: 11231761
    Abstract: Power monitoring circuitry is provided to monitor an input system power profile of processing tasks executing on a processing platform. An input is provided to receive from the processing platform, a processing system signal indicating a power being consumed by the processing platform. A counter is provided to store a count value corresponding to an accumulated number or amount of times that a warning threshold condition associated with a warning threshold value is satisfied by the received processing system signal in a count-accumulation time interval. The count value is supplied to a power control circuit of the processing platform via a bus in response to a read request from the power control circuit, the power control circuit being responsive to the count value to control a performance level of the processing platform.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Philip Lehwalder, Robert Santucci, Tod Schiff
  • Method and apparatus for efficient loop processing in a graphics hardware front end
    Patent number: 11232531
    Abstract: Various embodiments enable loop processing in a command processing block of the graphics hardware. Such hardware may include a processor including a command buffer, and a graphics command parser. The graphics command parser to load graphics commands from the command buffer, parse a first graphics command, store a loop count value associated with the first graphics command, parse a second graphics command and store a loop wrap address based on the second graphics command. The graphics command parser may execute a command sequence identified by the second graphics command, parse a third graphics command, the third graphics command identifying an end of the command sequence, set a new loop count value, and iteratively execute the command sequence using the loop wrap address based on the new loop count value.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 25, 2022
    Assignee: INTEL CORPORATION
    Inventors: Hema Chand Nalluri, Balaji Vembu, Peter Doyle, Michael Apodaca
  • Configuring display screen coordinates
    Patent number: 11231896
    Abstract: In one example, a system for screen configuration includes storage to store instructions and a processor. The processor is to execute the instructions to identify a relative position between a first display screen and a second display screen and to automatically adjust one or more coordinates of the second display screen in response to the relative position.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventor: Sean J. Lawrence
  • Multiplication-free approximation for neural networks and sparse coding
    Patent number: 11232273
    Abstract: Systems, apparatuses and methods may provide for replacing floating point matrix multiplication operations with an approximation algorithm or computation in applications that involve sparse codes and neural networks. The system may replace floating point matrix multiplication operations in sparse code applications and neural network applications with an approximation computation that applies an equivalent number of addition and/or subtraction operations.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Gautham Chinya, Shihao Ji, Arnab Paul
  • System and method for vector communication
    Patent number: 11232056
    Abstract: There is disclosed in an example, an endpoint apparatus for an interconnect, comprising: a mechanical and electrical interface to the interconnect; and one or more logic elements comprising an interface vector engine to: receive a first scalar transaction for the interface; determine that the first scalar transaction meets a criterion for vectorization; receive a second scalar transaction for the interface; determine that the second transaction meets the criterion for vectorization; vectorize the first scalar transaction and second scalar transaction into a vector transaction; and send the vector transaction via the electrical interface.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Wenqian Yu, Cunming Liang, Ping Yu, Shun Hao, Helin Zhang
  • Autonomous host detection for communication port management
    Patent number: 11231937
    Abstract: A method and system method for communication port management in a device. The method including enabling a set of communication ports in response to power up of the device, detecting connection at a port in the set of communication ports prior to operating system boot of the device, and connecting an external device to an operational component of the device in response to the connection at the port.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventor: Choon Gun Por
  • Invalid measurement indication in location measurement report
    Patent number: 11234129
    Abstract: This disclosure describes systems, methods, and devices related to an invalid location measurement report (LMR) indication. A device may identify a first null data packet (NDP) received from a first station device during, wherein the first NDP is used for channel sounding. The device may perform a time of arrival (ToA) calculation based on the NDP. The device may determine an invalid indication associated with the first NDP based on the ToA calculation. The device may generate an LMR comprising of the invalid measurement indication. The device may cause to send the LMR to the first device.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Feng Jiang, Qinghua Li, Jonathan Segev, Assaf Gurevitz, Danny Alexander, Xiaogang Chen
  • Memory controller with pre-loader
    Patent number: 11232035
    Abstract: Embodiments of the present disclosure relate to a controller that includes a monitor to determine an access pattern for a range of memory of a first computer memory device, and a pre-loader to pre-load a second computer memory device with a copy of a subset of the range of memory based at least in part on the access pattern, wherein the subset includes a plurality of cache lines. In some embodiments, the controller includes a specifier and the monitor determines the access pattern based at least in part on one or more configuration elements in the specifier. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij Doshi
  • Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload
    Patent number: 11231963
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 25, 2022
    Assignee: INTEL CORPORATION
    Inventors: Michael Behar, Moshe Maor, Ronen Gabbai, Roni Rosner, Zigi Walter, Oren Agam
  • System, apparatus and method for providing a fabric for an accelerator
    Patent number: 11231927
    Abstract: In one embodiment, an apparatus includes: an accelerator to execute instructions; an accelerator request decoder coupled to the accelerator to perform a first level decode of requests from the accelerator and direct the requests based on the first level decode, the accelerator request decoder including a memory map to identify a first address range associated with a local memory and a second address range associated with a system memory; and a non-coherent request router coupled to the accelerator request decoder to receive non-coherent requests from the accelerator request decoder and perform a second level decode of the non-coherent requests, the non-coherent request router to route first non-coherent requests to a sideband router of the first die and to direct second non-coherent requests to a computing die. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Robert D. Adler, Amit Kumar Srivastava, Aravindh Anantaraman
  • Vehicle with external audio speaker and microphone
    Patent number: 11231905
    Abstract: Various systems and methods for implementing a vehicle with an external speaker and microphone are described herein. A system includes an audio processor to receive audio data, the audio data sensed by a microphone array installed on the vehicle, the audio data generated by a source outside of the vehicle; an audio classification circuit to analyze the audio data using a machine learning technique to determine a sound event; and a vehicle interface to transmit a message to a vehicle control system, the message based on the sound event.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Hector Alfonso Cordourier Maruri, Sandra Coello Chavarin, Diego Mauricio Cortés Hernández, Rosa Jacqueline Sanchez Mesa, Lizbeth De la Mora Hernandez, Miquel Tlaxcalteco Matus
  • Method, apparatus and system for power supply policy exchange on a bus
    Patent number: 11232060
    Abstract: In one embodiment, an apparatus includes an input/output (I/O) circuit to communicate information at a selected voltage via an interconnect to which a plurality of devices may be coupled, and a host controller to couple to the interconnect. The host controller may include a supply voltage policy control circuit to initiate a supply voltage policy exchange with a first device to obtain a first supply voltage capability of the first device and to cause the I/O circuit and the first device to be configured to communicate via the interconnect at a first supply voltage based on the first supply voltage capability. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Kenneth P. Foust
  • Thread prefetch mechanism
    Patent number: 11232536
    Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 25, 2022
    Assignee: INTEL CORPORATION
    Inventors: Adam T. Lake, Guei-Yuan Lueh, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Abhishek R. Appu, Altug Koker, Subramaniam M. Maiyuran, Eric C. Samson, David J. Cowperthwaite, Zhi Wang, Kun Tian, David Puffer, Brian T. Lewis
  • Bottom-up fill dielectric materials for semiconductor structure fabrication and their methods of fabrication
    Patent number: 11232980
    Abstract: Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Florian Gstrein, Rami Hourani, Gopinath Bhimarasetti, James M. Blackwell
  • Memory prefetching in multiple GPU environment
    Patent number: 11232533
    Abstract: Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein the prefetcher of a GPU is prohibited from prefetching from a page that is not owned by the GPU or by the host processor.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 25, 2022
    Assignee: INTEL CORPORATION
    Inventors: Joydeep Ray, Aravindh Anantaraman, Valentin Andrei, Abhishek R. Appu, Nicolas Galoppo von Borries, Varghese George, Altug Koker, Elmoustapha Ould-Ahmed-Vall, Mike Macpherson, Subramaniam Maiyuran
  • Package on antenna package
    Patent number: 11233018
    Abstract: Wireless modules having a semiconductor package attached to an antenna package is disclosed. The semiconductor package may house one or more electronic components as a single die package and/or a system in a package (SiP) implementation. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The antenna package and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: January 25, 2022
    Assignee: INTEL CORPORATION
    Inventors: Sidharth Dalmia, Ana M. Yepes, Pouya Talebbeydokhti, Miroslav Baryakh, Omer Asaf
  • Layered substrate for microelectronic devices
    Patent number: 11232948
    Abstract: The present disclosure provides systems and methods for a layered substrate. A layered substrate may include a core comprising graphite. The layered substrate may also include a coating layer comprising a coating material that surrounds the core, wherein the coating material has a melting point that is greater than a melting point of silicon.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy
  • Embedded multi-die interconnect bridge having a molded region with through-mold vias
    Patent number: 11233009
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Praneeth Kumar Akkinepally, Frank Truong, Jason M. Gamba, Robert Alan May
  • Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
    Patent number: 11233152
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, William Hsu, Leonard P. Guler, Dax M. Crum, Tahir Ghani
  • Iris or other body part identification on a computing device
    Patent number: 11232316
    Abstract: An iris or other object detection method and apparatus are disclosed. In one embodiment, the method comprises sending image data to a display of a device that is captured with a first camera of the device with an indication to guide a user to position a body part of the user with respect to the display while the image data is being sent to the display, providing feedback to the user to indicate to the user that the body part is in position so that an image of the body part can be captured by a second camera of the device, capturing an image of the body part with the second camera, and performing recognition on the body part using the image.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Donghai Guo, Shuya Kevin Huang, Jun Liu
  • Double selector element for low voltage bipolar memory devices
    Patent number: 11233090
    Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Ravi Pillarisetty, Elijah V. Karpov, Brian S. Doyle, Abhishek A. Sharma
  • High-performance receiver architecture
    Patent number: 11233536
    Abstract: A wireless communication device can include an antenna array configured to receive a plurality of radio frequency (RF) signals, RF circuitry, and digital baseband receive circuitry. The RF circuitry is configured to process the plurality of RF signals received via the antenna array to generate a single RF signal. The digital baseband receive circuitry is coupled to the RF circuitry and is configured to generate a downconverted signal based on the single RF signal, amplify the downconverted signal to generate an amplified downconverted signal, and convert the amplified downconverted signal to generate a digital output signal for processing by a wireless modem. The digital baseband receive circuitry further includes at least a first filtering system configured to filter the downconverted signal prior to amplification.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Mohammed Alam, Yiwen Chen, Ricardo Fernandez, John J. Parkes, Jr., James Riches, Werner Schelmbauer, Daniel Schwartz, Michael David Vicker, Dong-Jun Yang
  • Reducing band-to-band tunneling in semiconductor devices
    Patent number: 11233148
    Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Jack T. Kavalieros, Seung Hoon Sung, Siddharth Chouksey, Harold W. Kennel, Dipanjan Basu, Ashish Agrawal, Glenn A. Glass, Tahir Ghani, Anand S. Murthy
  • Method and system of secured direct link set-up (DLS) for wireless networks
    Patent number: 11233633
    Abstract: Method and system of secured direct link set-up (DLS) for wireless networks. In accordance with aspects of the method, techniques are disclosed for setting up computationally secure direct links between stations in a wireless network in a manner that is computationally secure. A direct link comprising a new communication session is set up between first and second stations in a wireless local area network (WLAN) hosted by an access point (AP), the direct link comprising a new communication session. The AP generates a unique session key for the new communication session and transfers secured copies of the session key to each of the first and second stations in a manner under which only the first and second stations can obtain the session key. A security mechanism is then implemented on the unsecured direct link to secure the direct link between the first and second stations using a secure session key derived from the session key.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 25, 2022
    Assignee: INTEL CORPORATION
    Inventors: Jesse Walker, Shlomo Ovadia, Suman Sharma
  • Thermal management solutions for stacked integrated circuit devices using unidirectional heat transfer devices
    Patent number: 11234343
    Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device, and at least one unidirectional heat transfer device between the first integrated circuit device and the second integrated circuit device. In one embodiment, the unidirectional heat transfer device may be oriented such that it has a higher conductivity in the direction of heat transfer from the first integrated circuit device to the second integrated circuit device than it does in the opposite direction. When the temperature of the second integrated circuit device rises above the temperature of the first integrated circuit device, the unidirectional heat transfer device will act as a thermal insulator, and when the temperature of the first integrated circuit device rises above the temperature of the second integrated circuit device, the unidirectional heat transfer device will act as a thermal conductor.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Semiconductor device
    Patent number: 11233027
    Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Deutschland GmbH
    Inventors: Christoph Kutter, Ewald Soutschek, Georg Meyer-Berg
  • Warpage mitigation structures created on substrate using high throughput additive manufacturing
    Patent number: 11233015
    Abstract: Device package and method of forming a device package are described. The device package has a substrate with dies disposed on the substrate. Each die has a bottom surface that is electrically coupled to the substrate and a top surface. The device package further includes a plurality of stiffeners disposed directly on the substrate. The stiffeners may be directly attached to a top surface of the substrate without an adhesive layer. The device package may include stiffeners with one or more different sizes and shapes, including at least one of a rectangular stiffener, a picture frame stiffener, a L-shaped stiffener, a H-shaped stiffener, and a round pillar stiffener. The device package may have the stiffeners disposed on the top surface of the substrate using a cold spray process. The device package may also include a mold layer formed around and over the dies, the stiffeners, and the substrate.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventor: Feras Eid
  • Polarization gate stack SRAM
    Patent number: 11232832
    Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Integration of high density cross-point memory and CMOS logic for high density low latency eNVM and eDRAM applications
    Patent number: 11233040
    Abstract: An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memory blocks including orthogonally arranged conductive lines, and memory elements at cross-sections of the conductive lines. A first plurality of sockets is on the first die adjacent to the memory blocks, the first plurality of sockets comprising a first plurality of pads that connect to at least a portion to the conductive lines of the corresponding memory block. A second die includes logic circuitry and a second plurality of sockets comprising a second plurality of pads at least partially aligned with positions of the first plurality of pads on the first die. A top of the first die and a top of the second die face one another, wherein the first plurality of pads are bonded with the second plurality pads to directly connect the cross-point memory array to the logic circuitry.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Brian S. Doyle, Ravi Pillarisetty, Yih Wang
  • Group III-nitride (III-N) devices with reduced contact resistance and their methods of fabrication
    Patent number: 11233053
    Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta
  • REAL-TIME MASK QUALITY PREDICTOR
    Publication number: 20220020156
    Abstract: An embodiment of an image processing apparatus may comprise one or more processors, memory coupled to the one or more processor to store image and mask data, and logic coupled to the one or more processors and the memory, the logic to capture a volumetric broadcast video signal in real-time and generate a sequence of frame images from the captured real-time volumetric broadcast video signal, segment an input image, which corresponds to a single frame of the sequence of frame images, to generate a mask image associated with the input image, and determine a mask quality score based on the input image and the associated mask image in real-time. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Fahim Mohammad, Joseph Batz, Nathan Segerlind, Itay Benou, Tzachi Hershkovich
  • STACKED THERMAL PROCESSING CHAMBER MODULES FOR REMOTE RADIATIVE HEATING IN SEMICONDUCTOR DEVICE MANUFACTURE
    Publication number: 20220020613
    Abstract: Stacked thermal process chamber module for remote radiative heating of semiconductor device workpieces. A stacked thermal process module may include a stack of thermal process chambers and one or more generators of electromagnetic radiation. The electromagnetic radiation may be transported from a generator remote from the process chambers through one or more waveguides, thereby minimizing the volume and/or cleanroom footprint of the stacked thermal process chamber module. A waveguide may terminate in a process chamber so that electromagnetic radiation delivered during a thermal process may be coupled into one or more materials of the workpiece. The radiative heating process may overcome many of the limitations of thermal process chambers that instead employ a local heat source located within a process chamber.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Ashutosh Sagar, Chao-Kai Liang, Miye Hopkins, Weimin Han, Robert James
  • INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING
    Publication number: 20220019431
    Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.
    Type: Application
    Filed: July 6, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • DYNAMIC LOAD BALANCING FOR VIDEO ANALYTICS PIPELINES
    Publication number: 20220021917
    Abstract: In one embodiment, an edge compute node comprises processing circuitry to: receive an incoming video stream captured by a camera, wherein the incoming video stream comprises a plurality of video segments; store the plurality of video segments in a receive buffer in a memory; perform a visual computing task on a first video segment in the receive buffer; detect a resource overload on the edge compute node; receive load information corresponding to a plurality of peer compute nodes; select a peer compute node to perform the visual computing task on a second video segment in the receive buffer; replicate the second video segment from the edge compute node to the peer compute node; and receive a compute result from the peer compute node, wherein the compute result is based on the peer compute node performing the visual computing task on the second video segment.
    Type: Application
    Filed: April 2, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Yi Zou, Mohammad Ataur Rahman Chowdhury
  • COMPOSABLE TRUSTED EXECUTION ENVIRONMENTS
    Publication number: 20220019667
    Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.
    Type: Application
    Filed: June 22, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Kapil Sood, Ioannis T. Schoinas, Yu-Yuan Chen, Raghunandan Makaram, David J. Harriman, Baiju Patel, Ronald Perez, Matthew E. Hoekstra, Reshma Lal
  • METHOD AND APPARATUS FOR ADAPTIVELY REDUCING ARTIFACTS IN BLOCK-CODED VIDEO
    Publication number: 20220021906
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 20, 2022
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula