Abstract: Methods, computer readable media, and apparatus for determining a receive (Rx) number of spatial streams (NSS) for different bandwidths (BWs) and modulation and control schemes (MCSs) are disclosed. An apparatus is disclosed comprising processing circuitry configured to decode a supported HE-MCS and a NSS set field, the supported HE-MSC and NSS set field received from an high-efficiency (HE) station. The processing circuitry may be further configured to determine a first maximum value of N receive (Rx) SS for a MCS and a bandwidth (BW), where the first maximum value of N Rx SS is equal to a largest number of Rx SS that supports the MCS for the BW as indicated by the supported HE-MCS and NSS set field; and, determine additional maximum values based on an operating mode (OM) notification frame, and a value of an OM control (OMC) field. Signaling for BW in 6 GHz is disclosed.

Abstract: An access point (AP) configured for wireless local area network (WLAN) sensing is configured to encode a trigger frame (TF) for transmission. The trigger frame allocates resource units (RUs) for receiving high-efficiency (HE) trigger-based (TB) physical-layer protocol data units (PPDUs) (HE TB PPDUs) from a plurality of client devices (non-AP STAs). The trigger frame may solicit each of the client devices to transmit an HE TB PPDU in accordance with an UL OFDMA technique or an UL MU-MIMO technique. The AP may decode the HE TB PPDUs received from the client devices and may estimate channel state information (CSI) for a radio link associated with each of the client devices based on an HE-LTF of an associated one of the HE-TB PPDUs received from one of the client devices. In accordance with these embodiments, the AP may process changes in the CSI of the radio links over time for a WLAN sensing application.

Abstract: Various systems and methods of establishing a trusted pairing relationship between IoT devices, through the exchange of authentication service proof of possession tokens, are described herein. In an example, a trusted pairing relationship is established between IoT devices, through access control and credential resources based on communication via intermediary devices and services. The IoT devices may request or receive access to or information from a resource based on the trusted relationship.

Abstract: Systems and techniques for efficient remote function execution in an information centric network (ICN) are described herein. For example, a requestor node may transmit an admission probe interest packet. Here, the admission probe interest packet includes a name that includes a function. The admission probe interest packet also includes a metric of a parameter of the function. In response, the requestor node may receive a manifest data packet. The manifest includes a metric of function execution at a node that created the manifest data packet. The manifest also includes a name of an implementation of the function. The requestor node may then determine that the metric of function execution meets a threshold and transmit an interest packet that includes the name of the implementation of the function.

Abstract: Example methods, apparatus, systems and articles of manufacture (e.g., non-transitory physical storage media) to provide trust topology selection for distributed transaction processing in computing environments are disclosed herein. Example distributed transaction processing nodes disclosed herein include a distributed transaction application to process a transaction in a computing environment based on at least one of a centralized trust topology or a diffuse trust topology. Disclosed example distributed transaction processing nodes also include a trusted execution environment to protect first data associated with a centralized trust topology and to protect second data associated with a diffuse trust topology. Disclosed example distributed transaction processing nodes further include a trust topology selector to selectively configure the distributed transaction application to use the at least one of the centralized trust topology or the diffuse trust topology to process the transaction.

Abstract: Systems and methods may provide for determining an amount of physical bend in an electronic device and comparing the amount of physical bend to a threshold. Additionally, a warning may be generated if the amount of physical bend exceeds the threshold. In one example, one or more values representing the amount of physical bend are stored to a nonvolatile memory on the device and retrieved in accordance with one or more of a diagnostic push event or a diagnostic pull event.

Abstract: Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand.

Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating an Enhanced Directional Multi-Gigabit (DMG) (EDMG) Physical Layer Protocol Data Unit (PPDU). For example, an EDMG wireless communication station (STA) may be configured to communicate an EDMG PPDU including a Channel Estimation Field (CEF) and/or a pilot sequence, which may be configured for an OFDM mode.

Abstract: Examples described herein relate to a network interface that includes an initiator device to determine a storage node associated with an access command based on an association between an address in the command and a storage node. The network interface can include a redirector to update the association based on messages from one or more remote storage nodes. The association can be based on a look-up table associating a namespace identifier with prefix string and object size. In some examples, the access command is compatible with NVMe over Fabrics. The initiator device can determine a remote direct memory access (RDMA) queue-pair (QP) lookup for use to perform the access command.

Abstract: Disclosed herein are antenna boards, integrated circuit (IC) packages, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an IC package having a die and a package substrate, and the package substrate has a recess therein; and an antenna patch, coupled to the package substrate, such that the antenna patch is over or at least partially in the recess.

Abstract: For example, an apparatus may include a segment parser to parse scrambled data bits of a PPDU into a first plurality of data bits and a second plurality of data bits, the PPDU to be transmitted in an OFDM transmission over an aggregated bandwidth comprising a first channel in a first frequency band and a second channel in a second frequency band; a first baseband processing block to encode and modulate the first plurality of data bits according to a first OFDM MCS for transmission over the first channel in the first frequency band; and a second baseband block to encode and modulate the second plurality of data bits according to a second OFDM MCS for transmission over the second channel in the second frequency band.

Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.

Abstract: Thin, multi-focal plane, augmented reality eyewear are disclosed. An example lens structure includes a two-layer waveguide including a first waveguide and a second waveguide. The two-layer waveguide produces a virtual object based on light from an image source. The two-layer waveguide causes the virtual object to appear at a first virtual object focal plane. The first waveguide propagates more of the light in a first wavelength range than in a second wavelength range. The second waveguide propagates more of the light in the second wavelength range than in the first wavelength range. The first wavelength range is associated with longer wavelengths than the second wavelength range. The lens structure further includes an optical lens to cause the virtual object to appear at a second virtual object focal plane associated with a shorter apparent distance from a user than the first virtual object focal plane.

Abstract: An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

Abstract: Examples described herein can be used to determine and suggest a computing resource allocation for a workload request made from an edge gateway. The computing resource allocation can be suggested using computing resources provided by an edge server cluster. Telemetry data and performance indicators of the workload request can be tracked and used to determine the computing resource allocation. Artificial intelligence (AI) and machine learning (ML) techniques can be used in connection with a neural network to accelerate determinations of suggested computing resource allocations based on hundreds to thousands (or more) of telemetry data in order to suggest a computing resource allocation. Suggestions made can be accepted or rejected by a resource allocation manager for the edge gateway and the edge server cluster.

Abstract: Disclosures herein may be directed to a method, technique, or apparatus directed to a computer-assisted or autonomous driving (CA/AD) vehicle that includes a system controller, disposed in a first CA/AD vehicle, to manage a collaborative three-dimensional (3-D) map of an environment around the first CA/AD vehicle, wherein the system controller is to receive, from another CA/AD vehicle proximate to the first CA/AD vehicle, an indication of at least a portion of another 3-D map of another environment around both the first CA/AD vehicle and the another CA/AD vehicle and incorporate the at least the portion of the 3-D map proximate to the first CA/AD vehicle and the another CA/AD vehicle into the 3-D map of the environment of the first CA/AD vehicle managed by the system controller.

Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.

Abstract: Embodiments disclosed herein include a lithographic patterning system and methods of using such a system to form a microelectronic device. The lithographic patterning system includes an actinic radiation source, a stage having a surface for supporting a substrate with a resist layer, and a prism with a first surface over the stage, where the first surface has a masked layer and is substantially parallel to the surface of the stage. The prism may have a second surface that is substantially parallel to the first surface. The first and second surfaces are flat surfaces. The prism is a monolithic prism-mask, where an optical path passes through the system and exits the first surface of the prism through the mask layer. The system may include a layer disposed between the mask and resist layers. The mask layer of the prism may pattern the resist layer without an isolated mask layer.

Abstract: A semiconductor package including a molded power delivery module arranged between a package substrate and a semiconductor chip and including a plurality of input conductive structures and a plurality of reference conductive structures, wherein the input conductive structures alternate between the plurality of reference conductive structures, wherein the input conductive structure is electrically coupled with a chip input voltage terminal and a package input voltage terminal, wherein each of the plurality of reference conductive structures are electrically coupled with a semiconductor chip reference terminal and a package reference terminal.

Abstract: Embodiments of processors, methods, and systems for a processor core supporting processor identification instruction spoofing are described. In an embodiment, a processor includes an instruction decoder and processor identification instruction spoofing logic. The processor identification spoofing logic is to respond to a processor identification instruction by reporting processor identification information from a processor identification spoofing data structure. The processor identification spoofing data structure is to include processor identification information of one or more other processors.

Abstract: A system and method of detecting and remediating attacks includes receiving operating system (OS) read/write data from an OS, the OS read/write data describing at least one of reads from and writes to a storage device over a file system interface of the OS; collecting storage device read/write data, the storage device read/write data describing at least one of reads from and writes to the storage device; comparing the OS read/write data to the storage device read/write data; and determining if there is a discrepancy between the OS read/write data and the storage device read/write data. If there is a discrepancy, determining if there is an anomaly detected between OS read/write data and the storage device read/write data. If there is an anomaly, causing a remediation action to be taken to stop a malware attack.

Abstract: Described herein are transistor arrangements fabricated by forming a metal gate cut as a trench that is non-selective to the gate sidewalls, in an etch process that can remove both the gate electrode materials and the surrounding dielectrics. Such an etch process may provide improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts. In addition, such a process may be used to provide power rails, if the trench of a metal gate cut is to be at least partially filled with an electrically conductive material. Because the electrically conductive material is in the trench and may be in between the fins, as opposed to being provided over the fins, such power rails may be referred to as “recessed.” Providing recessed power rails may provide improvements in terms of reduced metal line resistance and reduced voltage droop.

Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

Abstract: Embodiments may relate an x-ray filter. The x-ray filter may be configured to be positioned between an x-ray source output and a device under test (DUT) that is to be x-rayed. The x-ray filter may include at least 80% titanium (Ti) by weight. Other embodiments may be described or claimed.

Abstract: At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system cause the system to send a unique identifier to a license server, establish a secure channel based on the unique identifier, request a license for activating an appliance from a license server over the secure channel, receive license data from the license server over the secure channel; determine whether the license is valid, and activate the appliance in response to a determination that the license data is valid.

Abstract: Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

Abstract: Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

Abstract: Gallium nitride transistors having multiple threshold voltages are described. In an example, a transistor includes a gallium nitride layer over a substrate, a gate stack over the gallium nitride layer, a source region on a first side of the gate stack, and a drain region on a second side of the gate stack, the second side opposite the first side, wherein the gate stack has a gate length in a first direction extending from the source region to the drain region, the gate stack having a gate width in a second direction perpendicular to the first direction and parallel to the source region and the drain region. The transistor also includes a polarization layer beneath the gate stack and on the GaN layer, the polarization layer having a first portion having a first thickness under a first gate portion and a second thickness under a second gate portion.

Abstract: An example private processing pipeline may include: a masked decryption unit to perform a masked decryption operation transforming input data into masked decrypted data; a masked functional unit to produce a masked result by performing a masked operation on the masked decrypted data; and a masked encryption unit to perform a masked encryption operation transforming the masked result into an encrypted result.

Abstract: Methods, apparatus, systems and articles of manufacture for generating a three-dimensional (3D) model for 3D scene reconstruction are disclosed. An example apparatus includes a 3D scene generator to generate a 3D model for digital image scene reconstruction based on a trained generative model and a digital image captured in a real environment. An image simulator is to generate a simulated image based on the 3D model, the simulated image corresponding to the captured image. A discriminator is to apply a discriminative model to the simulated image to determine whether the simulated image is simulated.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a remote direct memory access (RDMA) message from a first virtual machine located on a first network element, determine that the RDMA message is destined for a second virtual machine that is located on the first network element, and use a local direct memory access engine to process the RDMA message, where the local direct memory access engine is located on the first network element. In an example, the electronic device can be further configured to determine that the RDMA message is destined for a third virtual machine on a second network element, wherein the second network element is different than the first network element and use an other device acceleration driver to process the RDMA message instead of the local direct memory access engine.

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

Abstract: Systems, apparatuses and methods may store a plurality of classes that represent a plurality of clusters in a cache. Each of the classes represents a group of the plurality of clusters and the plurality of clusters is in a first data format. The systems, apparatuses and methods further modify input data from a second data format to the first data format and conduct a similarity search based on the input data in the first data format to assign the input data to at least one class of the classes.

Abstract: Input images are partitioned into non-overlapping segments perpendicular to a disparity dimension of the input images. Each segment includes a contiguous region of pixels spanning from a first edge to a second edge of the image, with the two edges parallel to the disparity dimension. In some aspects, contiguous input image segments are assigned in a “round robin” manner to a set of sub-images. Each pair of input images generates a corresponding pair of sub-image sets. Semi-global matching processes are then performed on pairs of corresponding sub-images generated from each input image. The SGM processes may be run in parallel, reducing an elapsed time to generate respective disparity sub-maps. The disparity sub-maps are then combined to provide a single disparity map of equivalent size to the original two input images.

Abstract: Density-graded adhesion layers on conductive structures within a microelectronic package substrate are described. An example is a density-graded adhesion layer that includes a dense region proximate to a conductive structure that is surrounded by a less dense (or porous) region adjacent to an overlying dielectric layer. Providing such a graded adhesion layer can have a number of benefits, which can include providing both mechanical connections for improved adhesion with a surrounding dielectric layer and provide hermetic protection for the underlying conductive structure from corrosive species. The adhesion layer enables the conductive structure to maintain its as-formed smooth surface which in turn reduces insertion loss of signals transmitted through the conductive structure.

Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.

Abstract: A graphics processor is described that includes a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The multiprocessor can execute parallel threads of instructions associated with a command stream, where the multiprocessor includes a set of functional units to execute at least one of the parallel threads of the instructions. The set of functional units can include a mixed precision tensor processor to perform tensor computations. The functional units can also include circuitry to analyze statistics for output values of the tensor computations, determine a target format to convert the output values, the target format determined based on the statistics for the output values and a precision associated with a second layer of the neural network, and convert the output values to the target format.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a substrate, a semiconductor die thereon, electrically coupled to the substrate, and an interposer adapted to connect the substrate to a circuit board. The interposer can include a major surface, a recess in the major surface, a first plurality of interconnects passing through the interposer within the recess to electrically couple the substrate to a circuit board, and a second plurality of interconnects on the major surface of the interposer to electrically couple the substrate to the circuit board, wherein each of the second plurality of interconnects comprises a smaller cross-section than some of the first plurality of interconnects.

Abstract: Methods, apparatus, systems and articles of manufacture to optimize execution of a machine learning model are disclosed. An example apparatus includes a quantizer to quantize a layer of a model based on an execution constraint, the layer of the model represented by a matrix. A packer is to pack the quantized layer of the matrix to create a packed layer represented by a packed matrix, the packed matrix having non-zero values of the matrix grouped together along at least one of a row or a column of the matrix. A blocker is to block the packed layer into a blocked layer by dividing the non-zero values in the packed matrix into blocks. A fuser is to fuse the blocked layer into a pipeline. A packager is to package the pipeline into a binary.

Abstract: Embodiments described herein generally relate to phased array antenna systems or packages and techniques of making and using the systems and packages. A phased array antenna package may include a distributed phased array antenna comprising (1) a plurality of antenna sub-arrays, which may each include a plurality of antennas, (2) a plurality of Radio Frequency Dies (RFDs), each of the RFDs located proximate and electrically coupled by a trace of a plurality of traces to a corresponding antenna sub-array of the plurality of antenna sub-arrays, and (3) wherein each trace of the plurality of traces configured to electrically couple an antenna of the plurality of antennas to the RFD located proximate the antenna, wherein each trace of the plurality of traces is configured to transmit millimeter wave (mm-wave) radio signals, and wherein the plurality of traces are each of a substantially uniform length.

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Abstract: Embodiments include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a substrate, and a plurality of conductive features formed over the substrate. In an embodiment, a bilayer build-up layer is formed over the plurality of conductive features. In an embodiment, the bilayer build-up layer comprises a first dielectric layer and a second dielectric layer. In an embodiment, a surface of the first dielectric layer comprises depressions. In an embodiment, the second dielectric layer is disposed in the depressions of the surface of the first dielectric layer.

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

Abstract: Techniques directed to forming and using coupling mechanisms for substrates, semiconductor packages, and/or printed circuit boards are described. One technique includes forming a substrate (205) comprising: first and second interconnect pads (213A, 213B) in or on a build-up layer (203); and first and second interconnects (211A, 211B) on the first and second interconnect pads (213A, 213B). The first interconnect pad (213A) can be located at a lower position than the second interconnect pad (213B) with regard to a z-position. The techniques described herein can assist with minimizing or eliminating solder ball bridge defects (SBBDs) that may be creating during performance of coupling technique (e.g., a reflow process, etc.).

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

Abstract: An integrated circuit assembly including a first die including a device side and a backside opposite the device side; and a second die including a plurality of fluidly accessible channels therein, wherein the second die is coupled to a backside of the first die. A method of fabricating an integrated circuit assembly including coupling a first die to a second die, wherein the first die includes a device side and an opposite backside, wherein the device side includes a plurality of integrated circuits and wherein the second die includes a plurality of fluidly accessible channels therein.

Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.