Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type
  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Patent number: 10687434
    Abstract: Mechanisms for SAS-free cabling in Rack Scale Design (RSD) environments and associated methods, apparatus, and systems. Pooled compute drawers containing multiple compute nodes are coupled to pooled storage drawers using fabric infrastructure, such as Ethernet links and switches. The pooled storage drawers includes a storage distributor that is coupled to a plurality of storage devices and includes one or more fabric ports and a PCIe switch with multiple PCIe ports. Under one configuration, the PCIe ports are connected to one or more IO hubs including a PCIe switch coupled to multiple storage device interfaces that are coupled to the storage devices. In another configuration, the PCIe ports are connected directly to PCIe storage devices. The storage distributor implements a NVMe-oF server driver that interacts with an NVMe-oF client driver running on compute nodes or a fabric switch.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Patent number: 10687282
    Abstract: Embodiments of a low-power wake-up radio (LP-WUR) are generally described herein. In some embodiments, a wireless device is set to a first state or a second state, wherein in the first state the wireless device is configured to receive wake-up (WU) packets, and wherein in the second state the wireless device is configured to not receive WU packets, wherein the wireless device comprises a WLAN radio and a low-power wake-up radio (LP-WUR). In some embodiments, the wireless device is configured to receive a wake-up packet, turn on the WLAN radio and turn off the LP-WUR. In some embodiments, the wireless device is configured to turn off the WLAN radio and turn on the LP-WUR for power conservation. In some embodiments, the wireless device turns off the WLAN radio and turns off the LP-WUR, and can periodically turn on the LP-WUR radio for extreme power saving.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel IP Corporation
    Inventors: Po-Kai Huang, Robert J. Stacey, Minyoung Park
  • Patent number: 10687083
    Abstract: Techniques related to selecting restoration filter coefficients for 2-dimensional loop restoration filters for super resolution video coding are discussed. Such techniques include upscaling reconstructed video frames along only a first dimension and selecting filter coefficients for portions of the frame by an evaluation that, for each pixel of the portion, uses only pixel values that are aligned with the first dimension. Selection of filter coefficients for the second dimension may be skipped or made using only a subset of available filter coefficients.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Ximin Zhang, Sang-Hee Lee, Keith W. Rowe
  • Patent number: 10687127
    Abstract: Technologies for managing the efficiency of workload execution in a managed node include a managed node that includes one or more processors that each include multiple cores. The managed nodes is to execute threads of workloads assigned to the managed node, generate telemetry data indicative of an efficiency of execution of the threads, determine, as a function of the telemetry data, an adjustment to a configuration of the threads among the cores to increase the efficiency of the execution of the threads, and apply the determined adjustment. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Johan G. Van De Groenendaal, Mrittika Ganguli, Ahmad Yasin
  • Patent number: 10687185
    Abstract: The present disclosure provides for a V2X communication configuration based on geographical location. Configuring the V2X communication can include generating a partitioned cell communication area; determining a presence of a UE in a geographical location of the partitioned cell communication area, wherein the UE is associated with a vehicle; and configuring a UL communication between the UE and the V2X server based on the geographical location.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Mikhail Shilov, Alexey Khoryaev, Sergey Panteleev, Dmitry Belov
  • Patent number: 10687384
    Abstract: This disclosure describes systems, methods, and devices related to disconnecting Wi-Fi radios due to operation of collocated wireless technology on a same device. A device may identify a first beacon received from an access point (AP), the first beacon indicating a beacon interval and received using a Wi-Fi radio. The device may determine an expected time to receive a second beacon. The device may identify a first signal received from a non-Wi-Fi radio collocated with the Wi-Fi radio. The device may determine, based on the first signal, an indication of a transmission or a reception of a second signal by the second radio during a time which overlaps the beacon interval. The device may determine a failure to identify a second beacon during the beacon interval. The device may determine a counter and may determine, based on the counter, a connection status of the first radio with the AP.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Daniel Cohn, Nir Balaban, Oz Shalev
  • Patent number: 10684718
    Abstract: Particular embodiments described herein provide for a wearable electronic device, such as a bracelet, watch, wristband or armband that includes a circuit board coupled to a plurality of electronic components (which may include any type of components, elements, circuitry, etc.). One particular implementation of a wearable electronic device may include a strap portion and a display portion. The display portion may include a display; one or more input elements configured to receive one or more interactions that may be associated with: selecting a preconfigured message to communicate and selecting one or more other electronic devices to which to communicate a preconfigured message. The wearable electronic device may further include wireless communication circuitry configured to communicate a selected preconfigured message to one or more selected other electronic devices.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventor: Aleksander Magi
  • Patent number: 10686605
    Abstract: Technologies for providing shared immutable code among untrusting domains are provided. The untrusting domains may be cryptographically separated within a cloud computing service or environment. The shared immutable code may be a shared virtual machine monitor (sVMM) that is setup by system software to indicate that the sVMM code pages need integrity alone and should be protected with an integrity key associated with individual domains. This indication may be stored in page tables and carried over the memory bus to a cryptographic engine. The cryptographic engine may use this indication to protect the integrity of data before storing the data to memory. In order to ensure cryptographic isolation, integrity values may be generated using a domain-specific key ensuring that an attempt to modify the code by one domain is detected by a different domain. Other embodiments are described herein and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, David M. Durham
  • Patent number: 10687286
    Abstract: Embodiments of a high efficiency (HE) access point (HE AP) and HE station (HE STA) are generally described herein. The HE AP may transmit a frame that includes a transmit power envelope element to indicate local maximum transmit power constraints for an operating bandwidth of the HE AP on a per-segment basis. The operating bandwidth may be configurable for division into segments of a configurable segment size. The transmit power envelope element may include: a transmit power information field that includes: a local maximum transmit power count subfield that indicates the operating bandwidth, and a segment size subfield that indicates the segment size; and for each of the segments, a local maximum transmit power per segment field that indicates a local maximum transmit power for the segment.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: June 16, 2020
    Assignee: Intel IP Corporation
    Inventors: Laurent Cariou, Po-Kai Huang, Necati Canpolat, Ehud Reshef
  • Patent number: 10687054
    Abstract: Techniques related to video encoding that provide for a decoupled prediction and coding structure for improved performance are discussed. Such techniques include determining final partitioning decisions for blocks of a picture by evaluating intra modes for candidate partitions by comparing the candidate partitions to intra predicted partitions generated using only original pixel samples and evaluating inter modes for the candidate partitions by comparing the candidate partitions to search partitions including original pixel samples and encoding using the final partitioning decision.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Nader Mahdi, Chekib Nouira, Hassen Guermazi, Faouzi Kossentini
  • Patent number: 10687235
    Abstract: Embodiments of an access point (AP), station (STA) and methods of communication are generally described herein. The AP may transmit a trigger frame (TF) that indicates resource units (RUs) that are available for contention based access by STAs for a fine timing measurement (FTM) protocol. The AP may attempt to decode one or more initial fine timing measurement request (iFTMR) frames received in the indicated RUs. The AP may transmit a broadcast acknowledgement (ACK) frame that indicates whether at least one iFTMR frame was decoded. The AP may, for a decoded iFTMR frame: allocate the RU corresponding to the decoded iFTMR frame to a corresponding STA for the FTM protocol; and transmit, in the corresponding RU, an initial fine timing measurement (iFTM) frame that includes an identifier of the corresponding STA.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel IP Corporation
    Inventors: Ganesh Venkatesan, Chittabrata Ghosh
  • Patent number: 10686638
    Abstract: Communication signals using a first and a second frequency band in a wireless network is described herein. The first frequency band may be associated with a first beamwidth while the second frequency band may be associated with a second beamwidth. An apparatus may include receiver circuitry arranged to receive first signals in a first frequency band associated with a first beamwidth and second signals in a second frequency band associated with a second beamwidth, the first signals comprising a frame synchronization parameter and the second signals comprising frame alignment signals. The apparatus may further include processor circuitry coupled to the receiver circuitry, the processor circuitry arranged to activate or deactivate the receiver circuitry to receive the frame alignment signals based on the frame synchronization parameter. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Alexander Maltsev, Vadim Sergeyev, Alexei Davydov, Ali Sadri, Roman Maslennikov, Alexey Khoryaev
  • Patent number: 10686859
    Abstract: Embodiments include apparatuses, methods, and systems including a content scenario detection unit and a rate adjustment unit for the communication of a multimedia content. The multimedia content may include a low bitrate scenario and a high bitrate scenario. The content scenario detection unit may detect the low bitrate scenario of the multimedia content for a multimedia traffic when a transmitter is to generate a first window of one or more frames of the low bitrate scenario during a first time period at a first encoding rate. The rate adjustment unit may determine, based at least in part on the detection of the low bitrate scenario, a second encoding rate different from the first encoding rate. The transmitter may generate at the second encoding rate a second window of one or more frames of the low bitrate scenario during a second time period. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Sri Ranjan Srikantam, Prasanna Kumar Mandapadi Ramasubramanian, Khanh V. Nguyen, Linda S. Cline
  • Patent number: 10686628
    Abstract: Embodiments of an access point (AP), station (STA) and method of sounding are generally described herein. The AP may transmit, during a transmission opportunity (TXOP), a trigger frame (TF) to indicate that an STA is to transmit an uplink sounding packet during an uplink sounding period of the TXOP. The AP may attempt to detect the uplink sounding packet during the uplink sounding period. If the uplink sounding packet is not detected during the uplink sounding period, the AP may transmit a recovery packet to cause other STAs to determine a busy condition during the uplink sounding period. If the uplink sounding packet is detected during the uplink sounding period, the AP may determine a channel estimate for the STA based at least partly on the uplink sounding packet.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel IP Corporation
    Inventors: Yuval Amizur, Chittabrata Ghosh, Jonathan Segev, Feng Jiang, Qinghua Li, Nir Dvorecki, Robert J. Stacey
  • Patent number: 10683189
    Abstract: Processes, apparatuses, and systems associated with usage and contextual-based elevator operations management that have the capability to learn and to constantly adapt to usage patterns on a temporal basis through continuous monitoring of elevator journeys. An elevator journey may include a start and termination floor for an individual. Elevator journey data may be used to predict patterns of usage and maybe used, for example, to optimize the number of elevators operational at any time, determine the optimal parking position of each elevator, and/or determine an efficient allocation of elevators to groups or related floors.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Ruchir Saraswat, Nicholas P. Cowley, Richard J. Goldman
  • Patent number: 10682574
    Abstract: Various systems and methods for providing immersive gaming are provided herein. A portable computing system for providing an immersive experience comprises a display; a graphics unit to present the immersive experience to a user on the display; a communication subsystem to determine a resource level of a resource coupled to the portable computing system; wherein the graphics unit is to present a representation of the resource level to the user in the immersive experience; wherein the communication subsystem is to: detect that the resource was replaced with a replacement resource, the replacement caused by a real-world interaction with the resource by the user; and determine a replacement resource level of the replacement resource; and wherein the graphics unit is to present a representation of the replacement resource level in the immersive experience on the display.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Yoshifumi Nishi, Jessica Gullbrand
  • Patent number: 10684663
    Abstract: Systems, apparatuses and methods may provide for receiving indicator data associated with activity of a load. Additionally, an estimation of a rate of change of a current of the load with respect to time may be determined from the indicator data. Moreover, a boost signal may be selectively output to a voltage regulator when the estimation of the rate of change is greater than a first amount. The boost signal may be associated with an adjustment in an output voltage of the voltage regulator and the output voltage may be provided to the load.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Kelly Livingston, Federico Ardanaz, Dmitry Lukianchenko, Fuat Keceli, Jonathan Eastep
  • Patent number: 10684667
    Abstract: An apparatus is provided which comprises: a first circuitry to estimate variation of an internal impedance of a battery; a second circuitry to estimate a high power that the battery can supply for a first time-period, based on the estimated variation of the impedance of the battery; and a third circuitry to facilitate operation of one or more components of the apparatus in accordance with the estimated high power for the first time-period.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Naoki Matsumura, Brian C. Fritz, Andy Keates, Alexander B. Uan-Zo-Li
  • Patent number: 10686688
    Abstract: Techniques for reducing fragmentation in software-defined infrastructures are described. A compute node, including one or more processor circuits, may be configured to access one or more remote resources via a fabric, the compute node may be configured to receive a dynamic tolerated fragmentation for the one or more remote resources. The compute node may be configured to monitor the performance of the one or more remote resources. For example, the compute node may be configured to monitor if one or more of the monitored resources were to exceed a threshold bandwidth or latency range as defined by the dynamic tolerated fragmentation. The compute node may be configured to determine that the monitored performance of the one or more remote resources is outside a threshold defined by the dynamic tolerated fragmentation.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: June 16, 2020
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Susanne M. Balle, Daniel Rivas Barragan, John Chun Kwok Leung, Suraj Prabhakaran, Murugasamy K. Nachimuthu, Slawomir Putyrski
  • Patent number: 10684683
    Abstract: Technologies for natural language interactions with virtual personal assistant systems include a computing device configured to capture audio input, distort the audio input to produce a number of distorted audio variations, and perform speech recognition on the audio input and the distorted audio variants. The computing device selects a result from a large number of potential speech recognition results based on contextual information. The computing device may measure a user's engagement level by using an eye tracking sensor to determine whether the user is visually focused on an avatar rendered by the virtual personal assistant. The avatar may be rendered in a disengaged state, a ready state, or an engaged state based on the user engagement level. The avatar may be rendered as semitransparent in the disengaged state, and the transparency may be reduced in the ready state or the engaged state. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventor: William C. Deleeuw
  • Patent number: 10685081
    Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store data. The processor is to: store a first dataset on the memory; identify a plurality of bin sizes for compressing the first dataset; compute a plurality of performance costs associated with the plurality of bin sizes; identify a minimum performance cost of the plurality of performance costs; identify an optimal bin size based on the particular bin size associated with the minimum performance cost; partition the first dataset into a plurality of bins based on the optimal bin size; identify a plurality of bin counts associated with the plurality of bins; generate a second dataset based on the plurality of bin counts, wherein the second dataset is smaller than the first dataset; and store the second dataset on the memory, wherein the second dataset is stored using less memory space than the first dataset.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Rita Chattopadhyay, Ravindra V. Narkhede
  • Patent number: 10684696
    Abstract: A method of mapping user movements captured by a capture device external to a computing device, to inputs events on the computing device, may comprise executing an application on the computing device, using at least one processor of the computing device. The computing device may transmit video data of the application to a receiver device. The computing device may receive gesture data associated with the application, the gesture data based on movements of a user captured from a capture device communicatively coupled to the receiver device. The gesture data may be mapped to an input event on the computing device and data simulating the input event may be provided to a sensor on the computing device.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Veeramani, Ujwal Paidipathi, Ajit Prakash Joshi
  • Patent number: 10684963
    Abstract: System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Alexander Slota, James Coleman, Rajkumar Khandelwal, Anil Kumar
  • Patent number: 10684855
    Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Erdinc Ozturk, Wajdi K. Feghali, Gilbert M. Wolrich, Martin G. Dixon
  • Patent number: 10685097
    Abstract: An embodiment of a semiconductor apparatus may include technology to receive an application-related checkpoint request corresponding to a file of a file system stored on a persistent storage media, and determine one or more checkpoint operations internal to the persistent storage media to perform the application-related checkpoint request. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Vadim Sukhomlinov, Sanjeev N. Trika
  • Patent number: 10684891
    Abstract: A system according to an exemplary embodiment receives an operand descriptor identifying characteristics of a set of data elements referenced by an operand to be accessed from a set of locations in a memory, wherein the operand descriptor describes an ordering of the set of data elements and respective locations in the memory for each respective data element in the set of data elements. The system further accesses the set of data elements in the memory based on the operand descriptor.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventor: Chris Newburn
  • Patent number: 10685159
    Abstract: In some examples, systems and methods may be used to improve functional safety of analog or mixed-signal circuits, and, more specifically, to anomaly detection to help predict failures for mitigating catastrophic results of circuit failures. An example may include using a machine learning model trained to identify point anomalies, contextual or conditional anomalies, or collective anomalies in a set of time-series data collected from in-field detectors of the circuit. The machine learning models may be trained with data that has only normal data or has some anomalous data included in the data set. In an example, the data may include functional or design-for-feature (DFx) signal data received from an in-field detector on an analog component. A functional safety action may be triggered based on analysis of the functional or DFx signal data.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Fei Su, Prashant Goteti
  • Patent number: 10684854
    Abstract: An embodiment of the invention is a processor including execution circuitry to, in response to a decoded instruction, convert a half-precision floating-point value to a single-precision floating-point value and store the single-precision floating-point value in each of the plurality of element locations of a destination register. The processor also includes a decoder and the destination register. The decoder is to decode an instruction to generate the decoded instruction.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Robert Valentine, Mark Charney, Raanan Sade, Elmoustapha Ould-Ahmed-Vall, Jesus Corbal
  • Patent number: 10684984
    Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Eliezer Tamir, Ben-Zion Friedman
  • Patent number: 10684833
    Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Ruchira Sasanka, Karthik Raman, Konstantinos Krommydas
  • Patent number: 10684945
    Abstract: In one embodiment, an apparatus includes a page miss handler to receive a full address including a linear address portion having a linear address and a key identifier portion having a key identifier for a key. The page miss handler may insert an entry including this key identifier in a translation storage. The apparatus further may include a remapping table having a plurality of entries each to store information regarding a key identifier. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, David M. Durham
  • Patent number: 10685182
    Abstract: System and techniques for identifying novel information are described herein. A classified experience may be obtained. The classified experience may include a set of attributes. Memory counts of members of the set of attributes for a user may be obtained. A novelty score for the classified experience may be computed by comparing the set of attributes to the memory counts. The classified experience may be presented to the user when the novelty score meets a qualification criterion.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Ali Ashrafi, Chetan Patel
  • Patent number: 10684973
    Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
  • Patent number: 10685476
    Abstract: Embodiments described herein provide an apparatus comprising a processor to project voxels from a point cloud data set into an n-DoF space, and define successively less granular supervoxels at successively higher layer of abstraction in a view of the point cloud data set, and a memory communicatively coupled to the processor. Other embodiments may be described and claimed.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 16, 2020
    Assignee: INTEL CORPORATION
    Inventors: Itay Kaufman, Jonathan Distler, Tzach Ashkenazi, Maria Bortman
  • Patent number: 10684865
    Abstract: The present application is directed to access isolation for multi-operating system devices. In general, a device may be configured using firmware to accommodate more than one operating system (OS) operating concurrently on the device or to transition from one OS to another. An access isolation module (AIM) in the firmware may determine a device equipment configuration and may partition the equipment for use by multiple operating systems. The AIM may disable OS-based equipment sensing and may allocate at least a portion of the equipment to each OS using customized tables. When transitioning between operating systems, the AIM may help to ensure that information from one OS is not accessible to others. For example, the AIM may detect when a foreground OS is to be replaced by a background OS, and may protect (e.g., lockout or encrypt) the files of the foreground OS prior to the background OS becoming active.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Kevin Y. Li, Vincent J. Zimmer, Xiaohu Zhou, Ping Wu, Zijian You, Michael A. Rothman
  • Patent number: 10685504
    Abstract: A method for dynamically handling traffic data can include obtaining location data and sensor data corresponding to at least one object located in a traffic area. The location data and/or the sensor data then can be selectively blurred to preserve privacy or meet privacy regulations. The blurring may be implemented by adding noise to the location data and/or the sensor data. The blurred data may then be transmitted to another entity.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventor: Markus Dominik Mueck
  • Patent number: 10685262
    Abstract: Techniques related to implementing convolutional neural networks for object recognition are discussed. Such techniques may include generating a set of binary neural features via convolutional neural network layers based on input image data and applying a strong classifier to the set of binary neural features to generate an object label for the input image data.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Anbang Yao, Lin Xu, Jianguo Li, Yurong Chen
  • Patent number: 10685446
    Abstract: A system, article, and method of recurrent semantic segmentation for image processing by factoring historical semantic segmentation.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Shahar Fleishman, Naomi Ken Korem, Mark Kliger
  • Patent number: 10684858
    Abstract: Disclosed embodiments relate to an indirect memory fetch (IMF) unit. In one example, an apparatus includes circuitry to fetch and decode an instruction specifying a sparse operand array including N operands, and an index array including N contiguously-addressed indices. The apparatus further includes a processing engine associated with an IMF unit to respond to the decoded instruction by initializing the IMF unit to fetch the N operands in order, probing the IMF unit to determine that a fetched operand is ready to retrieve, retrieving the fetched operand from the IMF unit, and repeating the probing and retrieving until all N operands have been retrieved. The IMF unit, independent of the processing engine, is to fetch the N contiguously-addressed indices from the index array, use the N fetched indices to calculate memory addresses for the N operands, and issue a plurality of read requests to fetch the N operands in order.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur, Joshua B. Fryman
  • Patent number: 10685289
    Abstract: Techniques are disclosed for improving classification performance in supervised learning. In accordance with some embodiments, a multiclass support vector machine (SVM) having three or more classes may be converted to a plurality of binary problems that then may be reduced via one or more reduced-set methods. The resultant reduced-set (RS) vectors may be combined together in one or more joint lists, along with the original support vectors (SVs) of the different binary classes. Each binary problem may be re-trained using the joint list(s) by applying a reduction factor (RF) parameter to reduce the total quantity of RS vectors. In re-training, different kernel methods can be combined, in accordance with some embodiments. Reduction may be performed until desired classification performance is achieved. The disclosed techniques can be used, for example, to improve classification speed, accuracy, class prioritization, or a combination thereof, in the SVM training phase, in accordance with some embodiments.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventor: Koba Natroshvili
  • Patent number: 10685214
    Abstract: The present disclosure is directed to face detection window refinement using depth. Existing face detection systems may perform face detection by analyzing portions of visual data such as an image, video, etc. identified by sub-windows. These sub-windows are now determined only based on pixels, and thus may number in the millions. Consistent with the present disclosure, at least depth data may be utilized to refine the size and appropriateness of sub-windows that identify portions of the visual data to analyze during face detection, which may substantially reduce the number of sub-windows to be analyzed, the total data processing burden, etc. For example, at least one device may comprise user interface circuitry including capture circuitry to capture both visual data and depth data. Face detection circuitry in the at least one device may refine face detection by determining criteria for configuring the sub-windows that will be used in face detection.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Haibing Ren, Yimin Zhang, Sirui Yang, Wei Hu
  • Patent number: 10686482
    Abstract: A metal chassis for a mobile device is configured to transmit a signal of a wavelength. A first side of the chassis faces the inside of the mobile device and includes a first aperture that has a dimension that comprises a first subwavelength width of a slot in the chassis. A second side of the chassis faces free space and includes a second aperture that has a dimension that comprises a second subwavelength width of the slot in the chassis. A channel connects the first aperture and the second aperture. The slot has a length dimension and the channel may be centered along the length dimension. The channel is configured to support a transverse electromagnetic mode for propagation of the signal from the first aperture through the channel to the second aperture. As a part of a mobile device the chassis acts as a secondary radiator for the mobile device.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Yaniv Michaeli, Menashe Soffer, Omer Asaf, Ana M. Yepes, Manish A. Hiranandani, Anand S. Konanur
  • Patent number: 10685666
    Abstract: A mechanism is described for facilitating automatic gain adjustment in audio systems according to one embodiment. A method of embodiments, as described herein, includes determining status of one or more of gain settings, mute settings, and boost settings associated with one or more microphones based on a configuration of a computing device including a voice-enabled device. The method may further comprise recommending adjustment of microphone gain based on the configuration and the status of one or more of the gain, mute, and boost settings, and applying the recommended adjustment of the microphone gain.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: June 16, 2020
    Assignee: INTEL CORPORATION
    Inventors: Przemyslaw Maziewski, Adam Kupryjanow, Lukasz Kurylo, Pawel Trella
  • Patent number: 10686763
    Abstract: Various embodiments are generally directed to techniques to distribute encrypted packets among multiple cores in a load-balanced manner for further processing. An apparatus may include a processor component; a decryption component to decrypt an encrypted packet to generate a decrypted packet from the encrypted packet, the encrypted packet comprising a header that comprises at least one field of information; a hash component to generate a header hash from the at least one field of information during decryption of at least a portion of the encrypted packet by the decryption component, the header hash comprising a smaller quantity of bits than the at least one field of information; and a distribution component to select a first core of multiple cores coupled to the processor component based on the header hash and to transmit the decrypted packet to the first core from the processor component. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: June 16, 2020
    Assignee: INTEL CORPORATION
    Inventors: Tomasz Kantecki, Niall McDonnell
  • Patent number: 10686626
    Abstract: In one embodiment, an apparatus comprises a processor, wherein the processor is configured to: detect deployment context information for an edge gateway, wherein the deployment context information identifies a deployment environment of the edge gateway based on information from one or more sensors; transmit, via a communications network, the deployment context information for the edge gateway to a gateway management node; receive, via the communications network, a gateway configuration for the edge gateway from the gateway management node; and configure the edge gateway based on the gateway configuration.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Usman Sarwar, Anil Kumar, Lee Booi Lim
  • Patent number: 10685850
    Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Schuckman
  • Patent number: 10685332
    Abstract: Various techniques for performing contextual event scheduling with an event scheduling service are disclosed herein. In an example, data is processed at an event scheduling service, based on the use of a trained machine learning model that is specific to a user. This trained machine learning model is operated by the event scheduling service determine a proposed time and proposed scheduling parameters based on the contextual information, to identify a proposed event time and event scheduling parameters based on the model, the data indicating a user state, or external data. Further examples to evaluate user activity and identify schedule characteristics based on data inputs from a user's mobile computing device, wearable sensors, and external weather, traffic, or event data sources, are also disclosed.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Gili Ilan, Noam Sagi, Gil Sharon, Oded Vainas, Ronen Aharon Soffer
  • Patent number: 10685949
    Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Mauro Kobrinsky, Johanna Swan, Rajendra C. Dias
  • Patent number: 10685688
    Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Muhammad M. Khellah
  • Patent number: 10686007
    Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Hubert C. George, Adel A. Elsherbini, Lester Lampert, James S. Clarke, Ravi Pillarisetty, Zachary R. Yoscovits, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts