Abstract: Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a heat source on the substrate, and a heat pipe. The heat pipe includes a plurality of bumps that extend from the heat pipe towards the substrate but do not come into contact with the substrate. The bumps are configured to help mitigate radio frequency interference in the electronic device. More specifically, the bumps can be configured to provide a resonant frequency in a specific radio frequency band and act as a radio frequency filter.

Abstract: This disclosure describes systems, methods, and devices related to uplink (UL) null data packet (NDP) format for passive location. A device may cause to send a trigger frame that solicits poll response to one or more anchor stations involved in a passive ranging measurement. The device may identify one or more polling response frames received from the one or more anchor stations. The device may cause to send a trigger frame that solicits uplink null data packet (NDP) to the one or more anchor stations, wherein the uplink NDP comprises an indication of a high efficiency (HE) single user (SU) frame type.

Abstract: Techniques related to coding video using adaptive quantization rounding offsets for use in transform coefficient quantization are discussed. Such techniques may include determining the value of a quantization rounding offset for a picture of a video sequence based on evaluating a maximum coding bit limit of the picture, a quantization parameter of the picture, and parameters corresponding to the video.

Abstract: An apparatus comprising circuitry to buffer video data; and a DisplayPort Transmitter to communicate the video data to a DisplayPort Receiver via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH); and communicate a power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in respective low power states.

Abstract: An semiconductor manufacturing apparatus and method to smooth surfaces of discrete pads on a substrate. The method includes placing a surface of one of the discrete pads in registration with a first chamber of a set of chambers of a smoothing tool, the set corresponding to a smoothing cycle of the smoothing tool; etching, within the first chamber, a surface of one of the discrete pads to form an etch layer on the surface; placing the surface in registration with a second chamber of the set; after the etch, pumping gas and vapor from the surface within the second chamber; placing the surface in registration with a third chamber of the set; and applying heating to the surface in the third chamber to smooth the surface.

Abstract: Techniques related to optical flow estimation for equirectangular images are discussed. Such techniques include combining an optical flow map generated using an input pair of equirectangular images and an optical flow map generated using a transformed pair of equirectangular images rotated with respect to the input pair to move polar regions in the input pair to central regions in the transformed pair.

Abstract: For example, a wireless station may be configured to map a plurality of data symbols to Orthogonal Frequency-Division Multiplexing (OFDM) symbols in a plurality of spatial (space-time) streams, to map a plurality of modulated pilot sequences to the OFDM symbols according to a pilot mapping scheme, and to transmit an OFDM Multiple-Input-Multiple-Output (MIMO) transmission based on the plurality of spatial streams.

Abstract: An electronic device may comprise a first chassis, a second chassis, and a hinge assembly configured to rotatably couple the first and second chassis together. The hinge assembly may include a guide unit including a first guide member and a second guide member disposed on opposite sides of a hinge plane and spaced to define a passage area therebetween. The hinge assembly may further include a biasing member configured to move the guide unit such that the passage area of the guide unit traverses the hinge plane in a first direction as the first chassis rotates from a closed position to a fully rotated position. The electronic device may also include a heat carrying member having one end disposed in the first chassis, a second end disposed in the second chassis, and a middle portion extending through the passage area. The size of the passage area may remain fixed.

Abstract: Techniques related to capturing 3D faces using image and temporal tracking neural networks and modifying output video using the captured 3D faces are discussed. Such techniques include applying a first neural network to an input vector corresponding to a first video image having a representation of a human face to generate a morphable model parameter vector, applying a second neural network to an input vector corresponding to a first and second temporally subsequent to generate a morphable model parameter delta vector, generating a 3D face model of the human face using the morphable model parameter vector and the morphable model parameter delta vector, and generating output video using the 3D face model.

Abstract: Techniques related to synthesizing an image of a person in an unseen pose are discussed. Such techniques include detecting a body part occlusion for a body part in a representation of the person in a first image and, in response to the detected occlusion, projecting a representation of the body part from a second image having a different view into the first image. A geometric transformation based on a source pose of the person and a target pose is then applied to the merged image to generate a synthesized image comprising a representation of the person in the target pose.

Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.

Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.

Abstract: Systems, methods, and devices can include a processing engine implemented at least partially in hardware, the processing engine to process memory transactions; a memory element to index physical address and virtual address translations; and a memory controller logic implemented at least partially in hardware, the memory controller logic to receive an index from the processing engine, the index corresponding to a physical address and a virtual address; identify a physical address based on the received index; and provide the physical address to the processing engine. The processing engine can use the physical address for memory transactions in response to a streaming workload job request.

Abstract: Technology for a user equipment (UE) operable for wideband coverage enhancement is disclosed. The UE can decode downlink control information (DCI) received in a physical downlink control channel (PDCCH). The UE can identify a transport block size (TBS) scaling factor from the DCI. The UE can identify a repetition number from the DCI, wherein the repetition number configures the UE to receive or transmit one or more of data and control channel information that is repeated, in the time domain, a selected number of times based on the repetition number. The UE can encode one or more of data or control information, for transmission to a next generation node B (gNB), based on the TBS scaling factor and the repetition number.

Abstract: Technologies for audiovisual communication include an audiovisual server and a number of audiovisual client devices, including a presenter device and a number of audience devices. Each audience device captures an audiovisual stream and transmits the audiovisual stream to the audiovisual server. Each audience device also captures sensor input data such as eye tracking data or facial expression data and transmits abstracted sensor input data to the audiovisual server. The abstracted sensor input data may be based on the captured audiovisual stream. The audiovisual server determines an interestingness rating associated with each audience device based on the sensor input data, and selects one or more audiovisual streams based on the interestingness ratings. The audiovisual server transmits the selected audiovisual streams to the presenter device. The audiovisual server may update the interestingness rating algorithm based on feedback from the presenter device or the audience devices.

Abstract: This disclosure describes systems, methods, and devices related to synched group key rekeying. A device may determine a first security key used for group-addressed management frames. The device may perform a security key rekeying to use a second security key in place of the first security key. The device may cause to send the second security key to a first station device of one or more station devices. The device may cause to send a first beacon frame comprising a switch announcement information element (IE) associated with the second security key. The device may cause to send a second beacon frame, wherein the second beacon frame does not comprise the switch announcement IE. The device may determine to switch to the second security key based on the switch announcement IE.

Abstract: A semiconductor package comprises a controlled voltage domain (CVD) and a master voltage domain (MVD). The MVD comprises an error-tolerance control (ETC) circuit. A basic execution block in the CVD generates a basic output value, based on at least two input values. A test execution block in the CVD generates a test digital root, based on digital roots of the input values. A digital root comparator in the CVD determines whether a digital root of the basic output value matches the test digital root. An error reporter in the CVD sends an error report to the ETC circuit in response to a determination that the digital roots do not match. The ETC may automatically adjust at least one power characteristic of the CVD, based on the error report. Other embodiments are described and claimed.

Abstract: A processor includes a processing core; a filter register to store a first permissions filter; and a memory management unit (MMU), coupled to the processing core, the filter register and a first peripheral device associated with the first permissions filter, wherein the MMU comprises a logic circuit to manage a shared page table comprising entries corresponding to the processing core and the first peripheral device, wherein the logic circuit is to; receive a memory access request for a first page of memory from the first peripheral device; determine whether the set of permission bits of the first entry match a first combination of bits of the first permissions filter; grant the memory access request if the set of permission bits match the first combination of bits of the first permissions filter; and cause a page fault if the set of permission bits do not matching the first combination of bits.

Abstract: Embodiments of the invention include a piezo-electric mirror in an microelectronic package and methods of forming the package. According to an embodiment the microelectronic package may include an organic substrate with a cavity formed in the organic substrate. In some embodiments, an actuator is anchored to the organic substrate and extends over the cavity. For example, the actuator may include a first electrode and a piezo-electric layer formed on the first electrode. A second electrode may be formed on the piezo-electric layer. Additionally, a mirror may be formed on the actuator. Embodiments allow for the piezo-electric layer to be formed on an organic package substrate by using low temperature crystallization processes. For example, the piezo-electric layer may be deposited in an amorphous state. Thereafter, a laser annealing process that includes a pulsed laser may be used to crystallize the piezo-electric layer.

Abstract: A memory controller is described. The memory controller includes a register to collectively track row active commands sent to multiple memory chip banks of a memory rank.

Abstract: The present disclosure relates to a dynamically composable computing system comprising a computing fabric with a plurality of different disaggregated computing hardware resources having respective hardware characteristics. A resource manager has access to the respective hardware characteristics of the different disaggregated computing hardware resources and is configured to assemble a composite computing node by selecting one or more disaggregated computing hardware resources with respective hardware characteristics meeting requirements of an application to be executed on the composite computing node. An orchestrator is configured to schedule the application using the assembled composite computing node.

Abstract: Systems and method are disclosed for monitoring processor performance. Embodiments described relate to differentiating function performance by input parameters. In one embodiment, a method includes configuring a counter contained in a processor to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value, configuring a precise event based sampling (PEBS) handler circuit to generate and store a PEBS record into a PEBS memory buffer after at least one overflow, the PEBS record containing at least one stack entry read from a stack after the at least one overflow, enabling the PEBS handler circuit to generate and store the PEBS record after the at least one overflow, generating and storing the PEBS record into the PEBS memory buffer after the at least one overflow; and storing contents of the PEBS memory buffer to a PEBS trace file in a memory.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Abstract: An apparatus to facilitate a tracking of surface properties is disclosed. The apparatus includes one or more processors to receive a memory request, access a virtual to virtual page table to retrieve an address storing surface properties metadata, and process the memory request, wherein the virtual to virtual page table provides a mapping between a main surface and an auxiliary surface including the surface properties metadata.

Abstract: A memory controller includes a sensor poller and a proportional integral controller (PIC) coupled to the sensor poller. The sensor poller is to obtain a temperature and a power of a memory module (MM) operated by the controller, and the PIC is to: dynamically set at least one bandwidth limit for the MM, based, at least in part, on a relationship between a temperature of the MM, a power of the MM and a bandwidth of the MM. The dynamically set bandwidth limit defines the power of the MM at which the MM operates for a predetermined temperature limit. A system includes a memory controller and a dual in-line memory module (DIMM) operated by it.

Abstract: The present disclosure provides confidential verification for FPGA code. Confidential verification for FPGA code can include receiving the policy from a cloud service provider (CSP) computing device, wherein the policy comprises a plurality of policy requirements used to determine whether to configure the FPGA using the code, receiving the code and the code encryption key from the user computing device, determining whether the code fulfills the plurality of policy requirements, and when the code fulfills the plurality of policy requirements encrypting and integrity protect the code using the code encryption key and providing the encrypted and integrity protected code to an accelerator loader to configure the FPGA using the code.

Abstract: Disclosed herein are maskless imaging tools and display systems that include piezoelectrically actuated mirrors and methods of forming such devices. The maskless imaging tool may include a light source. Additionally, the tool may include one or more piezoelectrically actuated mirrors for receiving light from the light source. The piezoelectrically actuated mirrors are actuatable about one or more axes to reflect the light from the light source to a workpiece positioned to receive light from the piezoelectrically actuated mirror. Disclosed herein is a maskless imaging tool that is a laser direct imaging lithography (LDIL) tool. The maskless imaging tool may also be a via-drill tool. Disclosed herein is also a piezoelectrically actuated mirror used in a projection system. For example, the projection system may be integrated into a pair of glasses.

Abstract: A semiconductor package apparatus may include technology to determine difference information between a parent node of a hierarchical data structure and a child node of the parent node, and store the difference information with the child node of the hierarchical data structure. Other embodiments are disclosed and claimed.

Abstract: Methods and apparatus for reducing energy consumed by drones during flight are disclosed. A drone includes a housing, a motor, receiver circuitry carried by the housing, and a route manager. The receiver circuitry is to receive airborne drone-generated wind data from an airborne drone located in an area within which a segment of a flight of the drone is to occur. The airborne drone-generated wind data is to be determined by an inertial measurement unit of the airborne drone. The route manager is to generate a route for the flight of the drone based on wind data, the wind data including the airborne drone-generated wind data. The route is to be followed by the drone during the flight. The route manager is to select at least one portion of the route to cause the drone to be at least partially propelled by wind to reduce energy consumed by the drone during the flight.

Abstract: Apparatuses, methods and storage medium associated with restricting current draw in wearable devices are disclosed herein. In embodiments, a wearable computing device may include a power source, one or more components coupled with each other and to the power source to perform wearable computing; and control circuitry coupled with the one or more components, the control circuitry to: identify a threshold selected based on a power consumption model of the wearable computing device; ascertain whether current draw from the power source is greater than the threshold; and restrict the current draw from the power source of the wearable computing device based on a signal output from one of the one or more components, in response to the current draw is ascertained to be greater than the threshold. Other embodiments may be disclosed or claimed.

Abstract: An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.

Abstract: Disclosed herein are embodiments of heat spreaders with interlocked inserts, and related devices and methods. In some embodiments, a heat spreader may include: a frame formed of a first material, wherein the frame includes an opening, a projection of the frame extends into the opening, and the projection has a top surface, a side surface, and a bottom surface; a recess having at least one sidewall formed by the frame; and an insert formed of a second material different from the first material, wherein the insert is disposed in the frame and in contact with the top surface, the side surface, and the bottom surface of the projection.

Abstract: An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

Abstract: An embodiment of a semiconductor package apparatus may include technology to create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory, identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and set a flag in the tracking structure to indicate that the memory location had the identified write request. Other embodiments are disclosed and claimed.

Abstract: Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit. During hardware emulation operations, an emulation host may be used to coordinate testing of the DUT on the programmable device. Circuit design tools may be used to extract parasitics from the ASIC design, compute low-level interconnect delays, convert the interconnect delays to higher-level port-to-port delays, convert the port-to-port delays to timing constraints, and generate corresponding configuration data for programming the programmable integrated circuit to emulate the ASIC design. The programmable integrated circuit may then be tested for functional and performance integrity.

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

Abstract: A processor includes a processing core to identify a code comprising a plurality of instructions to be executed in the architecturally-protected environment, determine that a first physical memory page stored in the architecturally-protected memory matches a first virtual memory page referenced by a first instruction of the plurality of instructions, generate a first address mapping between a first address of the first virtual memory page and a second address of the first physical memory page, store, in the cache memory, the address translation data structure comprising the first address mapping, and execute the code by retrieving the first address mapping in the address translation data structures to be executed in the architecturally-protected environment, determine that a first physical memory page stored in the architecturally-protected memory matches a first virtual memory page referenced by a first instruction of the plurality of instructions, generate a first address mapping between a first address of

Abstract: A system and method for distributed computing including a compute node having a graphics processing unit (GPU) to execute tasks of a distributed computing job. A distributed-computing programming framework executes the tasks on the compute node. A GPU-daemon process shares GPU resources between the tasks executing on the GPU of the compute node.

Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.

Abstract: A general-purpose graphics processor comprising a first set of compute units, a second set of compute units, and a memory coupled with the first set of compute units and the second set of compute units is described. The memory is configured to merge a first read request to an address block of the memory with a second read request to the address block of the memory to reduce a number of memory accesses to a memory bank associated with the address block. The graphics processor can also include a memory arbiter that can multicast merged reads to the compute units associated with the merged reads.

Abstract: Methods, apparatus, and system to compress a data file to form a compressed data file. The data file may be used to configure control of hardware, such as peripheral hardware. The compressed data file may be stored locally or transmitted to another computer device. The compressed data file may be stored in a flash memory. The compressed data file may require less space in flash memory components, relative to flash memory suitable to hold the (original, pre-compressed) data file. Compression and/or decompression may be performed by, for example, a flash memory controller. The compressed data file may be decompressed dynamically, on an as-needed basis, to provide code for execution by a processor and/or to configure a computer device to use hardware or other components. Other software and hardware components do not need to be aware that the data file is compressed in the flash memory.

Abstract: Semiconductor package assemblies and semiconductor packages incorporating an impedance-boosting channel between a transmitter die and a receiver die are described. In an example, a semiconductor package includes a package substrate incorporating the impedance-boosting channel having a first arc segment connected to the transmitter die and a second arc segment connected to the receiver die. The arc segments extend around respective vertical axes passing through a transmitter die electrical bump and a receiver die electrical bump, respectively. Accordingly, the arc segments introduce an inductive circuitry to increase signal integrity of an electrical signal sent from the transmitter die to the receiver die.

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.

Abstract: An apparatus is provided which includes: a first stack including a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, and a second stack including the middle and upper layers with one of the insulator layers therebetween. In an example, a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers. The apparatus further includes a first via over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween. The apparatus further includes a second via over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer. In an example, the second via is isolated from a sidewall of the upper layer by a spacer.

Abstract: Provided are a computer product, method, and system to virtualize target system storage resources as virtual target storage resources. Target storage resources available at a target system are discovered over a network. A configuration is determined of virtual target storage resources mapping to the target storage resources for a host node. The configuration is registered with a virtual target. The configuration maps the virtual target storage resources to the target storage resources at the target system and an access control list of the host node allowed to access the virtual target storage resources. A query is received from the host node for the target storage resources the host node is permitted to access according to the access control list. Host discovery information is returned to the requesting host node indicating the virtual target storage resources the requesting host node is provisioned to access from the virtual target.

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

Abstract: Technologies for network interface controllers (NICs) include a computing device having a NIC coupled to a root FPGA via an I/O link. The root FPGA is further coupled to multiple worker FPGAs by a serial link with each worker FPGA. The NIC may receive a remote direct memory access (RDMA) message from a remote host and send the RDMA message to the root FPGA via the I/O link. The root FPGA determines a target FPGA based on a memory address of the RDMA message. Each FPGA is associated with a part of a unified address space. If the target FPGA is a worker FPGA, the root FPGA sends the RDMA message to the worker FPGA via the corresponding serial link, and the worker FPGA processes the RDMA message. If the root FPGA is the target, the root FPGA may process the RDMA message. Other embodiments are described and claimed.

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

Abstract: Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a computing device. The virtualization environment includes a number of different virtual machines that are configured with a native graphics driver. The GPU scheduler receives GPU commands from the different virtual machines, dynamically selects a scheduling policy, and schedules the GPU commands for processing by the GPU.