Abstract: Briefly, in accordance with one or more embodiments, a fixed device synchronizes with a downlink channel of a network, acquires a master information block including a last system update time; and executes cell selection without acquiring other system information if the last system update time is before the last system access time. Furthermore, the fixed device may listen only for system information block messages that it needs, and ignore other system information blocks. A bitmap may indicate which system information block messages should be listed to for fixed devices, and which may be ignored. In some embodiments, one or more system information blocks may be designated for fixed devices.

Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).

Abstract: Systems and techniques for node-density aware interest packet forwarding in a dynamic ad hoc information centric network (ICN) are described herein. For example, a next interest packet to forward may be obtained at a network node. A time period to hold the next interest packet before forwarding may be calculated based on node density in the network. The node may then broadcast the next interest packet upon expiration of a timer set to the time period and started when the next interest packet was obtained.

Abstract: Embodiments include apparatuses, methods, and systems for computer assisted or autonomous driving. An apparatus may include a storage and a safety operation controller disposed in a computer assisted or autonomous driving vehicle. The storage may store a safety operation configuration and a list of safety operations to be performed on one or more device components. The safety operation configuration and the list of safety operations may be provided by a first party. The safety operation configuration may be used to configure selected ones of the list of safety operations by a second party different from the first party to obtain configured safety operations to be performed on the one or more device components. The safety operation controller may perform the configured safety operations on the one or more device components. Other embodiments may also be described and claimed.

Abstract: The present disclosure is directed to systems and methods for decomposing systolic array circuitry to provide a plurality of N×N systolic sub-array circuits, apportioning a first tensor or array into a plurality of N×M first input arrays, and apportioning a second tensor or array into a plurality of M×N second input arrays. Systolic array control circuitry transfers corresponding ones of the first input arrays and second input arrays to a respective one of the plurality of N×N systolic sub-array circuits. As the elements included in the first input array and the elements included in the second input array are transferred to the systolic sub-array, the systolic sub-array performs one or more mathematical operations using the first and the second input arrays. The systems and methods beneficially improve the usage of the systolic array circuitry thereby advantageously reducing the number of clock cycles needed to perform a given number of calculations.

Abstract: Apparatus, systems, or methods for mixed reality are disclosed herein. An apparatus may include an optical structure, a display structure, and a controller coupled to the optical structure and the display structure. The optical structure may be controlled by a first electrical signal to act as a transparent glass to present a natural view, or to act as a magnifying glass to present a virtual view. The display structure may be controlled by a second electrical signal to act as an opaque display or a transparent display. In addition, the controller may control the apparatus to operate in at least an AR mode to interlace the natural view and the virtual view. Other embodiments may also be described and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to establish communication between a first stationary unit and one or more vehicles, combine sensor data from the first stationary unit and at least one source outside the first stationary unit, generate an environmental map based on the combined sensor data, divide the environmental map into two or more map segments, and broadcast the two or more map segments. Other embodiments are disclosed and claimed.

Abstract: In embodiments, an apparatus for computing includes a protection key register (PKR) having 2N bits, where N is an integer, to store a plurality of permission entries corresponding to protected memory domains, and a protected memory domain controller, coupled to the PKR. In embodiments, the memory domain controller is to: obtain protection key (PK) bits from a page table entry for a target page address; obtain one or more additional PK bits from a target linear memory address; and combine the PK bits and the additional PK bits to form a PK domain number to index into the plurality of permission entries in the PKR to obtain a permission entry for a protected memory domain.

Abstract: In an example, an apparatus comprises a plurality of compute engines; and logic, at least partially including hardware logic, to detect a cache line conflict in a last-level cache (LLC) communicatively coupled to the plurality of compute engines; and implement context-based eviction policy to determine a cache way in the cache to evict in order to resolve the cache line conflict. Other embodiments are also disclosed and claimed.

Abstract: Techniques and mechanisms for communicating compiled software instructions via a network, wherein the compiled instructions are to execute a kernel process of a network device. In an embodiment, a first node of a network receives a kernel source code from a second node of the network. The first node compiles the kernel source code to generate a kernel binary code, which is provided to the second node. Based on the kernel binary code being communicated to the second node, a software developer is able to perform a simulation that facilitates the development of an application binary code. The first node subsequently receives the application binary and an indication that the application binary is to be executed with the kernel binary at the first node. In some embodiments, the first node executes an application process and a kernel process to provide an application offload resource for another network node.

Abstract: Disclosed herein are techniques to provide a unified display stream for multiple modes of a display specification. The display stream can include a link layer control protocol packet comprising link control information inserted between a set number of packets comprising display data. A packet can comprise indications of display data for a single stream or multiple streams.

Abstract: A processor includes cores and instructions executable by at least one of the plurality of cores as a virtual machine monitor (VMM). To configure resources for a virtual machine (VM), the VMM is to: group the cores into cluster(s), where a subset of the cores is to execute the VM; create, within a buffer in memory, a data structure to store, for the subset, one or more entries, each entry including a cluster identifier and a bitmap. The bitmap identifies cores of the subset within a cluster corresponding to the cluster identifier. The VMM is further to write, to a virtual machine control structure (VMCS): a pointer to the data structure, wherein the pointer includes a physical address of the memory; and a number of the one or more entries in the data structure; and set, within the VMCS, a local interrupt controller pass-through field.

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine workload-related information for a persistent storage media and a cache memory, and aggregate a bandwidth of the persistent storage media and the cache memory based on the determined workload information. Other embodiments are disclosed and claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for an apparatus configured to provide I/O classification information in a distributed cloud storage system, in accordance with some embodiments. In one embodiment, the apparatus may include a partition scanner, to scan an image of a virtual disk associated with the storage system, to determine one or more partitions associated with the virtual disk; a file system scanner coupled with the partition scanner, to identify file systems associated with the determined partitions, to access files stored in the identified file systems; and I/O classifier coupled with the file system scanner, to generate I/O classification information associated with the accessed files. The I/O classification information provides characteristics of input-output operations performed on the virtual disk. Other embodiments may be described and/or claimed.

Abstract: A data processing system includes support for sub-page granular memory tags. The data processing system comprises at least one core, a memory controller responsive to the core, random access memory (RAM) responsive to the memory controller, and a memory protection module in the memory controller. The memory protection module enables the memory controller to use a memory tag value supplied as part of a memory address to protect data stored at a location that is based on a location value supplied as another part of the memory address. The data processing system also comprises an operating system (OS) which, when executed in the data processing system, manages swapping a page of data out of the RAM to non-volatile storage (NVS) by using a memory tag map (MTM) to apply memory tags to respective subpages within the page being swapped out. Other embodiments are described and claimed.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: There is disclosed a system, including apparatus, methods and computer programs, for running native software applications (apps) and HTML5 web-based apps on a computing device, particularly a mobile computing device, in a multitasking mode of operation. In one embodiment, touch screen displays having one or more browsers are adapted to run one or more HTML5 apps, and receive input from hand gestures. One or more software modules execute on the operating system and are responsive to a dragging gesture applied to an HTML5 app displayed in a full screen mode, to subdivide the screen display and display the HTML5 app in one of the subdivided areas and display icons used to launch a second HTML5 app in a different one of the subdivided areas. The second HTML5 app is run concurrently with the first HTML5 app in order to provide multi-tasking between the first and second apps.

Abstract: An apparatus includes a software parser to generate a plurality of abstract syntax trees based on a plurality of software files, the ASTs including subtrees corresponding to a plurality of functions of the software files, a subtree encoder to generate a plurality of code vectors representative of one or more semantic properties of the subtrees, a function identifier to determine a plurality of clusters for the subtrees and assign a cluster identifier and a function label to the subtrees, a tree database to store the subtrees and map the plurality of subtrees to respective ones of cluster identifiers and function names, and a processor to: train a model based on a feature vector and the plurality of clusters stored in the tree database and predict the cluster identifier for the subtrees, based on the trained model, to identify a name of the function.

Abstract: An integrated circuit that is capable of performing sequence alignment via dynamic programming methods is provided. The integrated circuit may include a linear systolic array having series-connected processing engines, each of which has a n-stage deep pipeline. The systolic array may align first and second sequences, wherein the first sequence is divided into multiple segments equal to the internal depth of the pipeline. The systolic array may compute matrix scores for these segments in parallel until the entire sequence matrix score is computed. The internal pipeline structure and a loopback memory within the systolic array are configured to take care of any required data dependencies in the computation of the matrix scores.

Abstract: Adder trees may be constructed for efficient packing of arithmetic operators into an integrated circuit. The operands of the trees may be truncated to pack an integer number of nodes per logic array block. As a result, arithmetic operations may pack more efficiently onto the integrated circuit while providing increased precision and performance.

Abstract: Beam measurement reporting circuitry is provided for a user equipment (UE) of a wireless telecommunications network. The beam measurement reporting circuitry receives from the network, beam measurement configuration data and measures signal qualities for a plurality of received beams originating from a beam source of the network (serving and neighbouring cells). Beam measurements are performed by the UE to facilitate identification of a non-zero integer, N, beams depending upon the signal quality measurements. The identified beams can be candidate beams for a handover. Circuitry for a NodeB is also provided. A UE, a NodeB and corresponding methods incorporating the beam measurement reporting circuitry and beam measurement configuration circuitry are also provided.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: In embodiments, an apparatus for safety collaboration in autonomous or semi-autonomous vehicles may include an input interface to obtain sensor data from one or more sensors of a computer-assisted or autonomous driving (CA/AD) vehicle, an output interface, and an analyzer coupled to the input and output interfaces to process the sensor data to identify an emergency condition of the CA/AD vehicle, and in response to the identified emergency condition, cause a communication interface of the CA/AD vehicle, via the output interface, to broadcast a request for assistance to be received by one or more nearby CA/AD vehicles. In embodiments, the apparatus may be disposed in the CA/AD vehicle.

Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.

Abstract: Automated methods and apparatuses for charging or fueling a vehicle include provision of a plurality of tags and a controller to a vehicle. The plurality of tags are respectively installed at a plurality of positions on a top face of a roof of the vehicle. The controller is configured to cause information about a charging or fueling port of the vehicle to be transmitted to a charging or fueling system of a charging or fueling station. The charging or fueling system, provided with a charging connector or fueling nozzle, and an imaging device, uses at least the information about the charging or fueling port and the plurality of positions of the plurality tags to determine a location of the charging or fueling port of the vehicle, to charge or fuel the vehicle.

Abstract: Embodiments of the invention include microelectronic devices, resonators, and methods of fabricating the microelectronic devices. In one embodiment, a microelectronic device includes a substrate and a plurality of cavities integrated with the substrate. A plurality of vertically oriented resonators are formed with each resonator being positioned in a cavity. Each resonator includes a crystalline or single crystal piezoelectric film.

Abstract: Described herein are techniques for dealing with the problem of security vulnerabilities in computer software due to undefined behavior that may be exploited by attackers. A machine learning (ML) model is used for detecting an exploit execution within a given trace of application execution. In a specific embodiment, the ML model identifies whether there is any gadget or gadget-chain execution at branch points of a subject program.

Abstract: A method and apparatus including a cache controller coupled to a cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage of the cache controller to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs the combining and splitting of the plurality of cache access request by a second stage of the cache controller, and applies the plurality of cache access requests to the cache memory at line speed.

Abstract: Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch tessellations for the sub-patches. More particularly, systems, apparatuses and methods may provide a way to diverge tessellation sizes to a configurable size within an interior region of a patch or sub-patches based on a position of each of the tessellations. The systems, apparatuses and methods may determine a number of tessellation factors to use based on one or more of a level of granularity of one or more domains of a scene to be digitally rendered, available computing capacity, or power consumption to compute the number of tessellation factors.

Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.

Abstract: Techniques are disclosed to facilitate cooperative mapping for safe and efficient trajectory planning and collision avoidance by allowing nearby agents to share contextual information. The described techniques also function to extend the mapping range of a single agent by leveraging observations made by multiple agents. Furthermore, the techniques as described herein function to reduce uncertainty in trajectory planning by allowing agents to “see” behind occlusions, thus taking advantage of observations made by neighboring agents from different points of view. An efficient hardware implementation of the system is also presented that leverages the methodologies as discussed herein.

Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.

Abstract: An apparatus is described. The apparatus includes a storage device controller having logic circuitry to apply a program voltage verification process for a first threshold level to a group of non volatile memory cells and correlate first program voltages for the group of non volatile memory cells determined from the process to a second threshold level to determine second program voltages for the second threshold level for the group of non volatile memory cells. The second threshold level is higher than the first threshold level.

Abstract: A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

Abstract: Memory field-effect transistors and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor substrate and a ferroelectric gate insulator of a memory field-effect transistor formed within a trench having walls defined by spacers and a base defined by the semiconductor substrate. The apparatus further includes a gate conductor formed on the ferroelectric gate insulator. The ferroelectric gate insulator is to separate a bottom surface of the gate conductor and the substrate.

Abstract: A micro-light emitting diode (LED) display panel and a method of forming the display panel, the micro-LED display panel having a monolithically grown micro-structure including a first color micro-LED that is a first color nanowire LED, and a second color micro-LED that is a second color nanowire LED.

Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

Abstract: Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.

Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

Abstract: Small-scale audio speakers of various shapes are installed in parent devices. Inner casings, and the surrounding vibration-damping zone often required between such casings and the surrounding parent-device walls, are omitted from the assembly. During integration with the parent device, each un-encased speaker and its signal lines are sealed into a single-walled enclosure that incorporates a parent-device wall as at least one side. The entire interior of the single-walled enclosure becomes a back volume for the speaker. The single-walled enclosure may incorporate seals at the speaker's audio-output aperture, at the pass-through for the signal lines, and at the interface between the parent-device wall(s) and the added side(s) constituting the single-walled enclosure. Optional adhesive-free sealing options include sliding tabs held by a snap-lock latch.

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

Abstract: A port of a computing device is to connect to another device over a link and use equalization logic to perform equalization of the link at a plurality of different data rates. The equalization logic may identify that the other device supports bypassing a sequential equalization mode, determine a maximum data rate supported by the devices on the link, and participate in equalization of the link at the maximum supported data rate before equalizing the link at one or more other data rates lower than the maximum supported data rate in the plurality of data rates.

Abstract: A computing apparatus for providing a node within a distributed network function, including: a hardware platform; a network interface to communicatively couple to at least one other peer node of the distributed network function; a distributor function including logic to operate on the hardware platform, including a hashing module configured to receive an incoming network packet via the network interface and perform on the incoming network packet a first-level hash of a two-level hash, the first level hash being a lightweight hash with respect to a second-level hash, the first level hash to deterministically direct a packet to one of the nodes of the distributed network function as a directed packet; and a denial of service (DoS) mitigation engine to receive notification of a DoS attack, identify a DoS packet via the first-level hash, and prevent the DoS packet from reaching the second-level hash.

Abstract: There is disclosed in an example, a fabric interface device, having: a fabric interconnect to communicatively couple to a fabric; service level agreement (SLA) input logic to receive an SLA data structure from a controller, the SLA data structure providing an end-to-end SLA for a resource flow provided by a plurality of resources, and comprising QoS metrics for the resources; and SLA output logic to propagate the QoS metrics out to the resources via the fabric interconnect.

Abstract: Described herein is a data processing system comprising a memory device to store a multisample render target and a general-purpose graphics processor comprising a multisample antialiasing compressor and a multisample render cache. The multisample render target can store color data for a set of sample locations of each pixel in a set of pixels. The multisample antialiasing compressor can apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels. The multisample render cache can store color data generated for the set of sample locations of the first pixel in the set of pixels. Color data evicted from the multisample render cache is stored to the multisample render target.

Abstract: An optical system can include a optical receiver comprising an optical waveguide, an optical lid adjacent the waveguide, and a reflective surface proximate an output of the optical waveguide to direct light from the waveguide towards an output of the optical lid. The optical system can also include a photodetector (PD) die comprising a substrate, a concave mirror, and a photodetector. The concave mirror is formed on a first side of the substrate and the photodetector is disposed on a second side of the substrate, the first side opposite the second side, wherein the photodetector is disposed on the second side of the PD die offset from the optical axis of the optical element.

Abstract: A system comprising an interface to access a network slice power consumption parameter for a network slice comprising a logical network between two endpoints through a plurality of physical computing platforms; and a controller comprising circuitry, the controller to specify operating parameters for a plurality of hardware resources of a first physical computing platform in accordance with the network slice power consumption parameter.

Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.

Abstract: Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a double word with saturation; computing a dot product of bytes and accumulating in to a dword with saturation, where the input bytes can be signed or unsigned and the dword accumulation has output saturation; etc.