Abstract: Methods and systems herein provide better downlink (DL) data throughput for cell-edge stations (CE STAs). The systems enable protection from a third-party collision during a wideband DL data transmission to the cell edge STA, when the wideband control frame, such as clear-to-send (CTS) or acknowledge (ACK), transmission from a cell edge STA cannot reach the AP. This process can be achieved by designing a new wideband control frame comprising: a legacy preamble sent over the primary 20 MHz channel that can be decoded by the legacy STAs, a new preamble sent over the primary 20 MHz channel that can be used to identify the new wideband control frame (this new preamble has the total signal bandwidth information for the rest of the packet following the new preamble); and duplicate legacy control packets set over the total bandwidth indicated in the new preamble (the legacy control packets can be decoded by the legacy STAs).

Abstract: In embodiments, Internet of Things (IoT) devices may be organized according to an IoT device hierarchy, which may include parent and/or child associations between resources associated with IoT devices and/or with groupings of IoT devices. IoT devices wishing to support an IoT device hierarchy may utilize an extended IoT device resource model which provides for IoT device hierarchy information and interfaces to be provided by supporting IoT devices. A supporting resource may have one or more parent properties and/or child properties which may identify, respectively, parent or child resources which are associated with the resource. In various embodiments, these parent properties and/or child properties may include uniform resource identifiers (URI). A supporting resource may also identify an interface type for a hierarchical access interface, through which one or more descendant resources may be accessed through a single command. Other embodiments may be descried and/or claimed.

Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.

Abstract: A communication device for a vehicular radio communications includes one or more processors configured to identify a plurality of vehicular communication devices that form a cluster of cooperating vehicular communication devices, determine channel resource allocations for the plurality of vehicular communication devices that includes channel resources allocated for a first vehicular radio communication technology and channel resources allocated for a second vehicular radio communication technology, and transmit the channel resource allocation to the plurality of vehicular communication devices.

Abstract: A wireless communication device includes a memory, and a processing circuitry coupled to the memory. The processing circuitry is to process a wake-up radio (WUR) frame transmitted by an Access Point (AP), the WUR frame comprising a medium access control (MAC) header and a frame body, the MAC header comprising a Frame Control field, an Address field, and a Type Dependent (TD) Control field, wherein the Frame Control field comprises a Type field; determine, based on a value of the Type field, that the WUR frame is a WUR Discovery frame; determine an identifier (ID) of the AP from the WUR Discovery frame; and in response to a determination that the WUR frame is a WUR Discovery frame, cause a Primary Connectivity Radio (PCR) corresponding to the wireless communication device to communicate with the AP based on the WUR Discovery frame.

Abstract: In one embodiment, an apparatus comprises an antenna to receive one or more radio signals, wherein the antenna is associated with a proximity-based access portal. The apparatus further comprises a processor to: detect, based on the one or more radio signals, an access request from a first device, wherein the access request comprises a request to access the proximity-based access portal using an access token associated with an authorized device; determine, based on the one or more radio signals, that the first device is within a particular proximity of the proximity-based access portal; obtain a first motion history associated with movement detected near the proximity-based access portal; obtain a second motion history associated with movement detected by the authorized device; and determine, based on the first motion history and the second motion history, whether the movement detected near the proximity-based access portal matches the movement detected by the authorized device.

Abstract: Embodiments are directed towards apparatuses, methods, and systems for a connector having a housing body to couple a dual in-line memory module (DIMM) to a printed circuit board (PCB). In embodiments, the housing body includes first and second opposing ends of the connector and a first and a second latch coupled at the respective first and second opposing ends of the connector to engage the DIMM. In embodiments, the first and the second opposing ends have respective first and second heights relative to a height of the housing body to allow the DIMM to be inserted or removed at an angle when disengaged from the first and second latch. In embodiments, one or more of the latches are removably coupled to the connector and/or can be rotated into a lay-flat position to allow the DIMM to be removed at an angle. Additional embodiments may be described and claimed.

Abstract: Techniques for providing cooperative communication via multicast communications are disclosed. An example apparatus comprises a memory and processing circuitry coupled to the memory. The processing circuitry is configured to generate a multicast group address based, at least in part, on a geographical region of the apparatus, and broadcast the multicast group address to allow cooperative communication enabled devices to join a multicast group corresponding to the multicast group address. The apparatus is also configured to receive requests from the cooperative communication enabled devices to join the multicast group. The apparatus is also configured to transmit messages to the multicast group via multicast communications.

Abstract: A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device.

Abstract: Disclosed embodiments include a catalyst-doped mold interconnect system, where activated catalyst particles that line via and trace corridors, are used for electroless-plating formation of both liners and vias and traces that also electrolessly plate onto the liners. Photolithographically formed interconnects can be mingled with laser-ablation form-factor vias and traces within a single stratum of a catalyst doped mold interconnect system.

Abstract: In an embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect according to a bus clock signal; a first receiver to receive second information from at least one of the plurality of devices via the interconnect according to the bus clock signal; and a clock generation circuit to generate the bus clock signal having an asymmetric duty cycle. Other embodiments are described and claimed.

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Abstract: An apparatus, method, system and computer readable medium for video tracking. An exemplar crop is selected to be tracked in an initial frame of a video. Bayesian optimization is applied with each subsequent frame of the video by building a surrogate model of an objective function using Gaussian Process Regression (GPR) based on similarity scores of candidate crops collected from a search space in a current frame of the video. A next candidate crop in the search space is determined using an acquisition function. The next candidate crop is compared to the exemplar crop using a Siamese neural network. Comparisons of new candidate crops to the exemplar crop are made using the Siamese neural network until the exemplar crop has been found in the current frame. The new candidate crops are selected based on an updated surrogate model.

Abstract: An electrical characterization and fault isolation probe can include a cable, a connector, and a coating over a portion of the cable. The cable can have a first conductor having a first impedance, a second conductor having a second impedance, and a dielectric surrounding the first conductor and electrically isolating the first conductor from the second conductor. The connector can physically couple to, and be in electrical communication with, the cable. The connector can include a first electrical communication pathway and a second electrical communication pathway. The first electrical communication pathway can be electrically isolated from the second electrical communication pathway. The first electrical communication pathway can be in electrical communication with the first conductor. The second electrical communication pathway can be in electrical communication with the second conductor. The connector can have a fifth impedance.

Abstract: Various systems and methods for managing an ambient user interface on a laptop are described herein. A laptop device includes an upper portion including a display device and a lower portion coupled to the upper portion with a hinge mechanism, the lower portion including a reflective surface. When the laptop device is closed and the upper portion abuts the lower portion, the display device is configured to display images that are reflected on the reflective surface.

Abstract: A multiple mode display apparatus and methods of use. An apparatus includes a display surface with a first and a second display area. A housing pivotally attached with the display proximate a first edge of the housing is displaceable from a coplanar position with the surface of the display device to a position wherein an angle of at least 90 degrees between the surface of the display and the housing is formed along said first edge. In the first position, the first display area is visible and activated to receive user input or to display output. The second display area is covered by the housing and placed in a mode of reduced power consumption. In the second position, the second display area is visible and activated to display output.

Abstract: Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.

Abstract: Technologies for managing interoperable high definition (HD) maps for autonomous vehicles includes a HD map server to distribute interoperable HD map tiles to various autonomous vehicles, each of which may be configured to utilize proprietary HD map tiles of different propriety formats. As such, each of the autonomous vehicles is configured to translate the interoperable HD map tile to the proprietary format used by that particular vehicle. Additionally, each autonomous vehicle may submit crowd-sourced sensor data to the interoperable HD map server using a universal data set by converting the sensor data to a universal data structure.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce temperature of a networked device. An example apparatus includes, a temperature threshold monitor to identify a temperature condition associated with the device, a window information retriever to retrieve a current value of a network receive capacity parameter, and a window adjustor to reduce the temperature of the device by generating a modified network receive capacity parameter, the modified network receive capacity parameter based on a ratio of the current value of the network receive capacity parameter and a decrease factor.

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a processing array including multiple compute blocks, each compute block including multiple processing clusters and a thread dispatch unit to dispatch threads of a workload to the multiple compute blocks based on a parallelism metric, wherein the thread dispatch unit, based on the parallelism metric, is to perform one of a first operation and a second operation, the first operation to distribute threads across the multiple compute blocks and the second operation is to concentrate threads within one of the multiple compute blocks.

Abstract: Wrap-around contact structures for semiconductor fins, and methods of fabricating wrap-around contact structures for semiconductor fins, are described. In an example, an integrated circuit structure includes a semiconductor fin having a first portion protruding through a trench isolation region. A gate structure is over a top and along sidewalls of the first portion of the semiconductor fin. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor fin. The epitaxial structure has substantially vertical sidewalls in alignment with the second portion of the semiconductor fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor fin and along the substantially vertical sidewalls of the epitaxial structure.

Abstract: Apparatus and method for correcting image regions following upsampling or frame interpolation. For example, one embodiment of an apparatus comprises a machine-learning engine to evaluate at least a first image in a sequence of images generated by a real-time interactive application, the machine learning engine to responsively use previously learned data to generate an upsampled or interpolated image comprising a plurality of pixel patches. In one embodiment, each pixel patch is associated with a confidence value reflecting how accurately the pixel patch was generated by the machine learning engine. A selective ray tracing engine identifies a first pixel patch to be corrected based a first confidence value corresponding to the first pixel patch being lower than a threshold and performs ray tracing operations on a first portion of the first image to generate a corrected first pixel patch.

Abstract: Apparatuses including general-purpose graphics processing units and graphics multiprocessors that exploit queues or transitional buffers for improved low-latency high-bandwidth on-die data retrieval are disclosed. In one embodiment, a graphics multiprocessor includes at least one compute engine to provide a request, a queue or transitional buffer, and logic coupled to the queue or transitional buffer. The logic is configured to cause a request to be transferred to a queue or transitional buffer for temporary storage without processing the request and to determine whether the queue or transitional buffer has a predetermined amount of storage capacity.

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

Abstract: An embodiment includes an apparatus comprising: first and second semiconductor fins that are parallel to each other; a first gate, on the first fin, including a first gate portion between the first and second fins; a second gate, on the second fin, including a second gate portion between the first and second fins; a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer connecting the first and second oxide layers to each other; and an insulation material between the first and second gate portions; wherein the first, second, and third oxide layers each include an oxide material and the insulation material does not include the oxide material. Other embodiments are described herein.

Abstract: Disclosed are electronic device assemblies, computing devices, and related methods. An electronic device assembly or a computing device includes an interlayer dielectric region between a first region and a second region, a conductive interlayer structure formed through the interlayer dielectric region, and a barrier region formed around the conductive interlayer structure. The conductive interlayer structure includes a composition of Ml-Alm—X1n—X2p—Cq—Or, wherein M comprises a metal selected from one or more of titanium, zirconium, hafnium, tantalum, niobium and vanadium; C comprises carbon; O comprises oxygen; X1 comprises gallium; X2 comprises indium; and l, m, n, p, q and r represent an atomic percent of an element in the barrier region that can be 0 percent, but n and p cannot both be 0 percent. A method includes forming the barrier region within a passage through the interlayer dielectric region.

Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.

Abstract: A mechanism is described for facilitating smart geo-fencing-based payment transactions according to one embodiment. A method, as described herein, includes detecting, by one or more capturing/sensing components of a data processing device, a first computing device within proximity of a geo-fenced location. The method further includes receiving detection information relating to the detection of the first computing device, authenticating at least one of the first computing device and the geo-fenced location, and interfacing the first computing device with a second computing device. The method may further include facilitating a payment transaction, where the payment transaction includes payment of a monetary amount from the second computing device to the first computing device, and executing the payment transaction.

Abstract: A spin orbit torque (SOT) memory device includes a MTJ device on a SOT electrode, where a first portion of the SOT electrode extends beyond a sidewall of the MTJ by a first length that is no greater than a height of the MTJ, and where a second portion of the first electrode extends from the sidewall and under the MTJ by a second length that is no greater than a width of the MTJ. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet.

Abstract: To maintain the integrity of electrical contacts at a build-up layer of a chip package, while reducing electrical interference caused by a chip connected to the build-up layer, the chip package can include a stiffener formed from an electrically conductive material and positioned between the chip and the build-up layer. The chip can electrically connect to the build-up layer through electrical connections that extend through the stiffener. Compared with a stiffener that extends only over a single chip of the chip package, the present stiffener can help prevent warpage or other mechanical deformities that can degrade electrical contacts away from the chip at the build-up layer. Compared with a stiffener that extends only over an area away from the chip, such as a peripheral area, the present stiffener can help reduce electrical interference in an area of the build-up layer near the chip.

Abstract: System and techniques for gateway assisted diagnostics and repair are described herein. A request for assistance may be received from a client device at a gateway device attached to a local area network (LAN) and a wide area network (WAN). The request for assistance may include an indication of an event experienced by the client device. The request for assistance may be forwarded to a management controller of the gateway device. Instructions may be transmitted to the client device via the LAN for resolving the event experienced by the client device.

Abstract: Systems and methods include establishing a cryptographically secure communication between an application module and an audio module. The application module is configured to execute on an information-handling machine, and the audio module is coupled to the information-handling machine. The establishment of the cryptographically secure communication may be at least partially facilitated by a mutually trusted module.

Abstract: Technologies for network interface controllers (NICs) include a compute sled and an accelerator sled in communication over a network. The accelerator sled configures a virtual switch endpoint associated with a remote direct memory access (RDMA) server instance that is associated with a field-programmable gate array (FPGA) of the accelerator sled. The accelerator sled updates local software defined networking (SDN) tables with a virtual tunnel associated with the virtual switch endpoint and a remote compute sled. A virtual switch of the accelerator sled switches virtual tunnel traffic from the remote compute sled to the RDMA server instance, which transfers data to or from the FPGA. The compute sled also updates a local SDN table with the virtual tunnel, and a virtual switch of the compute sled switches virtual tunnel traffic to or from the accelerator sled. Other embodiments are described and claimed.

Abstract: An apparatus and method are described for a multithreaded-aware performance monitor of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each performance monitor counter to count baseline events during processing of the multiple instruction threads; and a performance monitor circuit to determine whether multiple threads are concurrently generating the same baseline event and, if so, then the performance monitor circuit to distribute the count of the baseline event for only one of the multiple threads in each processor cycle for which the multiple threads are active and the baseline event applies to.

Abstract: An apparatus comprises a first circuitry to perform, in response to a first message from an operating system, a first process to place a computer device in a first operating mode, store state information in a volatile memory of the computer device, and start a timer for a time-out period for performing the first process. First components of the computer device are in a low power state. A second circuitry to detect, after the time-out period, a failure of the first process. A third circuitry to perform, in response to the detected failure of the first process, a second process to place the computer device in a second operating mode and store state information in a non-volatile memory of the computer device. The volatile memory is operational in the first operating mode and is in a low power state in the second operating mode.

Abstract: An apparatus to facilitate metrics and security-based accelerator service rescheduling and auto-scaling using a programmable network device is disclosed. The apparatus includes processors to collect metrics corresponding to communication links between microservices of a service managed by a service mesh; determine, based on analysis of the metrics, that a workload of the service can be accelerated by offload to a hardware accelerator device; generate a scaling request to cause the hardware accelerator device to be allocated to a cluster of hardware devices configured for the service; cause the scaling request to be transmitted to a programmable network device managing the hardware accelerator device, the programmable network device to allocate the hardware accelerator device to the cluster and to register the hardware accelerator device with the service mesh; and schedule the workload of the service to the hardware accelerator device.

Abstract: A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

Abstract: A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.

Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline based at least in part on a first data bounds value stored in the metadata region, generate a first integrity value based on the first portion of the cacheline, and prevent the memory access operation in response to determining that the first integrity value does not correspond to a second integrity value stored in the metadata region.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a virtual reality engine to create a virtual environment for a user, a communication engine in communication with at least one reference point pad on the user, and a haptic actuator location engine to determine a position of one or more removable haptic pads on the user using sensor data from the one or more removable haptic pads and the at least one reference point pad. In an example, the sensor data is motion data from an accelerometer, gyroscope, or some other sensor(s) to detect movement of the one or more removable haptic pads and the at least one reference point pad.

Abstract: Telemetry information in the form of platform telemetry, virtualization layer telemetry, and application telemetry can be used to estimate power consumption of a software entity, such as a virtual machine, container, application, or network slice. A controller can take various actions based on software entity power consumption information. If a power limit of an integrated circuit component is exceeded, the controller can reduce the power consumption of a software entity or move the software entity to another integrated circuit component to reduce the power consumption of the integrated circuit component. The controller can determine a total software entity power consumption for software entities associated with a user entity and take actions to keep the total software entity power consumption within a power budget.

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to read utilization-related information for a resource from a memory shared with a processor in response to a request from the processor for the resource, and schedule utilization of the resource based at least in part on the utilization-related information for the resource. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses, and methods to mitigate effects of glitch attacks on a broadcast communication bus are provided. The voltage levels of the communication bus are repeatedly sampled to identify glitch attacks. The voltage level on the communication bus can be overdriven or overwritten to either corrupt received messages or correct received messages.

Abstract: A system for generating a robustness score for hardware components, nodes, and clusters of nodes in a computing infrastructure is provided. The system includes a memory and at least one processing device coupled to the memory. The processing device is to obtain first telemetry data associated with a selected portion of a computing infrastructure, and the selected portion includes a first node and a first hardware component. The processing device is further to obtain first metadata associated with the selected portion, input one or more telemetry inputs corresponding to the first telemetry data into a machine learning model, input one or more metadata inputs corresponding to the first metadata into the machine learning model, and generate, from the machine learning model, a first robustness score for the first hardware component representing a health state of the first hardware component.

Abstract: An apparatus of a computing system, the computing system, a method to be performed at the apparatus, and a machine-readable storage medium. The apparatus includes control circuitry to: perform a page walk operation on a page table structure of a pooled memory; based on the page walk operation, determine page table entries (PTEs) corresponding to a workload to be executed by the computing system; and during a time interval not including a page walk operation by the control circuitry, perform a plurality of sampling operations, individual ones of the sampling operations including determining PTE metadata corresponding to at least some of the PTEs.

Abstract: Providing multiple virtual processors (VPs) for a trusted domain (TD) includes creating a virtual processor control structure (VPCS) for one or more of a plurality of VPs of the TD of a processor in a computing system, the TD including a trust domain control structure (TDCS), the plurality of VPs having views into addresses of private memory of the TD, the VPCS for a VP including a secure extended page table (SEPT) for the VP; and for the VP, initializing the VPCS for the VP by copying selected entries of the TDCS to the SEPT of the VPCS, pointing a SEPT pointer to the VPCS, and setting an entry point for starting execution of the VP by the processor.

Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.

Abstract: Technologies for memory mirroring across an interconnect are disclosed. In the illustrative embodiment, a primary memory agent that controls a single memory channel can implement memory mirroring by sending mirrored memory operations to a secondary memory agent over an interconnect. In the illustrative embodiment, the secondary memory agent may not be aware that it is performing mirrored memory operations. The primary memory agent may handle error recovery, scrubbing, and failover to the secondary memory agent.