Abstract: Techniques are provided herein for forming interconnect structures, such as conductive vias or contacts, that are protected from subsequent processing that includes reactive gas or plasma. A conductive via or contact within an interconnect layer may be formed with a capping layer having a different material to protect the underlying metal material from reacting with certain reactive gas or plasma elements. In some examples, a ruthenium capping layer is formed over a copper via to protect the copper. Other capping layer materials may include tungsten, cobalt, or molybdenum. In some embodiments, the entire conductive via may be formed using one of ruthenium, tungsten, cobalt, or molybdenum, to avoid the use of more reactive metals, such as copper. The capping layer (or less reactive metals) are used to protect the via during a barrier layer doping process that uses a gas or plasma including a chalcogen element (e.g., sulfur and/or selenium).

Abstract: Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×1017 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 1017 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

Abstract: An apparatus to facilitate transparent network access controls for spatial accelerator device multi-tenancy is disclosed. The apparatus includes a secure device manager (SDM) to: establish a network-on-chip (NoC) communication path in the apparatus, the NoC communication path comprising a plurality of NoC nodes for ingress and egress of communications on the NoC communication path; for each NoC node of the NoC communication path, configure a programmable register of the NoC node to indicate a node group that the NoC node is assigned, the node group corresponding to a persona configured on the apparatus; determine whether a prefix of received data at the NoC node matches the node group indicated by the programmable register of the NoC; and responsive to determining that the prefix does not match the node group, discard the data from the NoC node.

Abstract: Techniques are provided for protecting integrated circuits from plasma-induced electrostatic discharge (ESD) using a carrier substrate with integrated junctions. According to some embodiments, the various metal features within an interconnect region above a plurality of semiconductor devices are electrically coupled to one or more conductive pads on a bonded carrier substrate. The conductive pads provide a contact to underlying doped regions within the carrier substrate that form one or more PN junctions. This provides the ability to electrically ground metal features in the interconnect region via the carrier substrate. Formation of additional interconnect layers such as those provided during far back end of line (FBEOL) processing, can proceed while causing less plasma-induced ESD damage to the integrated circuit, because the interconnect region is connected to ground of carrier substrate by way of PN junctions, thus providing a discharge path for charge that develops during subsequent processing.

Abstract: A leakage insensitive transistor includes a substrate, a source region, a drain region, a channel region between the source region and drain region, a gate dielectric on the channel region, first and second electrodes on the gate dielectric, and third and fourth electrodes on the substrate. The leakage insensitive transistor may be operated by applying a first logic signal to the first electrode, floating the second electrode of the FET, applying a second logic signal opposite the first logic signal to the third electrode, and floating the fourth electrode. A logic circuit may include multiple leakage insensitive transistors.

Abstract: In one embodiment, a state is encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.

Abstract: The apparatus of an edge computing node, a system, a method and a machine-readable medium. The apparatus includes a processor to perform rounds of federated machine learning training including: processing client reports from a plurality of clients of the edge computing network; selecting a candidate set of clients from the plurality of clients for an epoch of the federated machine learning training; causing a global model to be sent to the candidate set of clients; and performing the federated machine learning training on the candidate set of clients. The processor may perform rounds of federated machine learning training including: obtaining coded training data from each of the selected clients; and performing machine learning training on the coded training data.

Abstract: A microelectronic assembly is provided, comprising a first IC die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR) electrically coupled to the first IC die, a package substrate having inductors of the VR electrically coupled to the first IC die and the second IC die, and a mold compound between the first IC die and the package substrate. The VR receives power at a first voltage from the package substrate and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the second IC die is in the mold compound. In some embodiments, the mold compound and the second IC die are comprised in a discrete interposer electrically coupled to the first IC die with die-to-die interconnects and to the package substrate with die-to-package substrate interconnects.

Abstract: Devices and techniques related to implementing patch based video coding for machines are discussed. Such patch based video coding includes detecting regions of interest in a frame of video, extracting the detected regions of interest to one or more atlases absent the frame at a resolution not less than the resolution of the regions of interest, and encoding the one or more atlases to a bitstream.

Abstract: Techniques are provided herein to form semiconductor devices having different work function metals over different devices. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to gate-all-around (GAA) transistors. In an example, neighboring semiconductor devices each include a different work function to act as the device gate electrode for each semiconductor device. More specifically, a first semiconductor device may be a p-channel GAA transistor with a first work function metal around the various nanoribbons of the transistor, while the second neighboring semiconductor device may be an n-channel GAA transistor with a second work function metal around the various nanoribbons of the transistor. No portions of the first work function metal are present around the nanoribbons of the second semiconductor device and no portions of the second work function metal are present around the nanoribbons of the first semiconductor device.

Abstract: Techniques are provided herein to form semiconductor devices having gate tie-down structures between the device gate and a buried/backside power rail (BPR). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure on a semiconductor region. The semiconductor region can be, for example, a fin or a set of one or more nanowires or nanoribbons that extends between a source region and a drain region. A BPR structure is beneath a dielectric layer that is between the BPR structure and the conductive material of the gate structure. A portion of the conductive material also extends through the dielectric material to provide a conductive via between the gate structure and the underlying BPR structure. The conductive material may be, for example, work function and/or metal fill material of the gate electrode of the gate structure.

Abstract: One embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling operation via a mixed precision convolutional neural network, the set of processing resources including circuitry configured to receive, at an input block of a neural network model, history data, velocity data, and current frame data, pre-process the history data, velocity data, and current frame data to generate pre-processed data, provide the pre-processed data to a feature extraction network of the neural network model, process the pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, and generate an output image via an output block of the neural network model via direct reconstruction or kernel prediction.

Abstract: A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

Abstract: Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.

Abstract: This disclosure describes methods, apparatus, and systems related to enhanced Bluetooth triggering of device Wi-Fi radios. A device may determine a first Bluetooth data packet including transport data and an indication of a Wi-Fi service discovery, the transport data including a first sub-field and a second sub-field, the first sub-field indicating a length of the second sub-field, and the second sub-field indicating one or more Wi-Fi services supported by the device. A Bluetooth radio of the device may send the first Bluetooth data packet including an indication of a Wi-Fi service. The device may identify a second Bluetooth data packet received by the Bluetooth radio from a second device, the second Bluetooth data packet indicating that the Wi-Fi service is supported by the second device. The device may use a Wi-Fi radio to send one or more Wi-Fi frames associated with the Wi-Fi service to the second device.

Abstract: One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.

Abstract: Integrated circuit (IC) devices implementing bilayer memory stacking with compute logic circuits shared between bottom and top memory layers are disclosed. An example IC device includes a first IC structure that includes one or more memory layers but not necessarily compute logic circuits, the first IC structure being bonded with a second IC structure that includes at least one layer of compute logic circuits and further includes one or more memory layers stacked above the compute logic circuits. The first and second IC structures may be bonded so that the compute logic circuits of the second IC structure may be communicatively coupled to memory layers of both the first and second IC structures.

Abstract: One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

Abstract: A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.

Abstract: A graphics processor is provided that includes circuitry configured to receive, at an input block of a neural network model, a set of data including previous frame data, current frame data, velocity data, and jitter offset data. The neural network model is configured to generate a denoised, supersampled, and anti-aliased output image based on reliability metrics computed based on sample distribution data for samples within the current frame data.

Abstract: A method comprises receiving an image of an update for a software module, a rate parameter, an index parameter, and a public key, generating a 32-byte aligned string, computing a state parameter using the 32-byte aligned string, generating a modified message representative, computing a Merkle Tree root node, and in response to a determination that the Merkle Tree root node matches the public key, forwarding, to a remote device, the image of the update for a software module, the state parameter; and the modified message representative.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve boundary excursion detection. An example apparatus to improve boundary excursion detection includes a metadata extractor to parse a first control stream to extract embedded metadata, a metadata label resolver to classify a boundary term of the extracted embedded metadata, a candidate stream selector to identify candidate second control streams that include a boundary term that matches the classified boundary term of the first control stream, and a boundary vector calculator to improve boundary excursion detection by calculating a boundary vector factor based on respective ones of the candidate second control streams that include the classified boundary term.

Abstract: Technologies for addressing individual bits in memory include a device having a memory that includes partitions that each have tiles, in which each tile stores an individual bit. The device also includes circuitry to receive a request to access (e.g., read or write) a sequence of bits in a partition. The request specifies a logical row or column address. A corresponding tile is determined from the logical row or column address and for each bit in the sequence. The corresponding tile is accessed to read or write the bit therein.

Abstract: Technologies for user-assisted machine learning includes a compute device configured to request user assistance to classify sensor data in response to a determination that a confidence score associated with the classification of the sensor data is below a threshold value and/or if the classification of the sensor data is unknown. In an illustrative embodiment, the compute device is configured to communicate with an activity monitor device, such as a smart pet collar, to determine activities of the subject (e.g., a pet) based on classification data received from the smart pet collar.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein that mitigate hard-braking events. An example apparatus includes a world generator to generate a deep learning model to identify and categorize an object in a proximity of a vehicle, a data analyzer to determine a danger level associated with the object, the danger level indicative of a likelihood of a collision between the vehicle and the object, a vehicle response determiner to determine, based on the danger level, a response of the vehicle to avoid a collision with the object, and an instruction generator to transmit instructions to a steering system or a braking system of the vehicle based on the determined vehicle response.

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: An apparatus and method for scheduling threads on local and remote processing resources.

Abstract: Techniques for image-based search using touch controls are described. An apparatus may comprise: a processor circuit; a gesture component operative on the processor circuit to receive gesture information from a touch-sensitive screen displaying an image and generate a selection area corresponding to the gesture information; a capture component operative on the processor circuit to extract an image portion of the image corresponding to the selection area; and a search component operative on the processor circuit to perform an image-based search using the extracted image portion. Other embodiments are described and claimed.

Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve Doppler velocity estimation. An example apparatus is disclosed including a transmitter to transmit a first sweep signal at a first position in a first block of time during a transmit time sequence pattern, and transmit a second sweep signal at a second position in a second block of time during the transmit time sequence pattern, the second position different than the first position. The example apparatus also includes a velocity analyzer to determine a velocity and a direction of arrival of a target object identified during the transmit time sequence pattern.

Abstract: Embodiments described herein are generally directed to an improved vector normalization instruction. An embodiment of a method includes responsive to receipt by a GPU of a single instruction specifying a vector normalization operation to be performed on V vectors: (i) generating V squared length values, N at a time, by a first processing unit, by, for each N sets of inputs, each representing multiple component vectors for N of the vectors, performing N parallel dot product operations on the N sets of inputs. Generating V sets of outputs representing multiple normalized component vectors of the V vectors, N at a time, by a second processing unit, by, for each N squared length values of the V squared length values, performing N parallel operations on the N squared length values, wherein each of the N parallel operations implement a combination of a reciprocal square root function and a vector scaling function.

Abstract: Systems, methods, and apparatuses relating to performing logical operations on packed data elements and testing the results of that logical operation to generate a packed data resultant are described.

Abstract: An apparatus to facilitate memory data compression is disclosed. The apparatus includes a memory and having a plurality of banks to store main data and metadata associated with the main data and a memory management unit (MMU) coupled to the plurality of banks to perform a hash function to compute indices into virtual address locations in memory for the main data and the metadata and adjust the metadata virtual address locations to store each adjusted metadata virtual address location in a bank storing the associated main data.

Abstract: Described are mechanisms and methods for implementing highly configurable power delivery management policies. An apparatus may comprise a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may include a memory to store a first table having one or more first entries and to store a second table having one or more respectively corresponding second entries. The second circuitry may, upon the occurrence of an event, test a condition specified by an entry in the first table. The third circuitry may, upon the test of the condition having a positive result, evaluate a set of one or more parameters as specified by an entry in a second table corresponding with the entry in the first table. The fourth circuitry may initiate a power-management action based upon the evaluation of the set of one or more parameters.

Abstract: A mechanism is described for facilitating storage management for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting one or more components associated with machine learning, where the one or more components include memory and a processor coupled to the memory, and where the processor includes a graphics processor. The method may further include allocating a storage portion of the memory and a hardware portion of the processor to a machine learning training set, where the storage and hardware portions are precise for implementation and processing of the training set.

Abstract: A device may comprise: a storage for storing a reference output representing an output of an electrical circuit at a reference temperature; one or more processors, configured to: determine a temperature shift based on a comparison of an output of the electrical circuit sensed at a sensing temperature and the reference output; determine a plurality of coefficients of a model of the temperature shift, wherein the model implements one or more functions that associate the plurality of coefficients and a temperature with the temperature shift at the temperature.

Abstract: In connection with an access of content from a cache, a snoop request can be sent to one or more remote cache devices to determine if any other cache has a copy of the content. A link between the cache and the remote cache devices can include a snoop bypass device. The snoop bypass device can monitor content cached by the one or more remote devices on a cache line or coarser granularity. The snoop bypass device can respond to the snoop request with a negative indication based on a coarser granularity tracking of content of the one or more remote cache devices.

Abstract: Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

Abstract: The bandgap-less apparatus is a fast settling circuit (e.g., with settling time of less than 40 ns) that can leverage proportional-to-absolute-temperature only (PTAT-only) currents to generate a zero or substantially zero temperature coefficient, or even complementary-to-absolute-temperature (CTAT), reference current or voltage, without the need of a native CTAT component or bandgap diodes. The apparatus subtracts two different PTAT currents so that the resulting current is zero-TC. The resulting current is a reference current. The resulting current can be converted to a reference voltage.

Abstract: An apparatus for testing integrated circuits (ICs) , includes a first thermal contact structure having a first surface to interface with a heat source and an opposing second surface to interface with a device under test (DUT). A second thermal contact structure is above the first thermal contact structure and separated therefrom by a variable-resistance thermal interface (VRTI) structure operable to couple or decouple the first and second thermal contact structures from one another. The VRTI structure has a maximal thermal conductivity associated with a first state, and a minimal thermal conductivity associated with a second state.

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device. In some embodiments, the apparatus comprises an interconnect partially adjacent to the structure of the magnetic junction, wherein the interconnect comprises a spin orbit material, wherein the interconnect has a pocket comprising non-spin orbit material, wherein the pocket is adjacent to the magnet of the magnetic junction. In some embodiments, the non-spin orbit material comprises metal which includes one or more of: Cu, Al, Ag, or Au.

Abstract: Packets may be compressed based on predictive analyses. For example, in one embodiment, it is determined that an explicit value for a particular header field can be inferred by the receiver agent, a packet header is constructed that either omits the header field or includes a differential value for the header field in lieu of the explicit value for the header field. The packet header may be decompressed upon receipt by deriving the explicit value for the particular header field.

Abstract: Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes.

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.

Abstract: An integrated circuit includes a base comprising an insulating dielectric. A plurality of conductive lines extends vertically above the base in a spaced-apart arrangement, the plurality including a first conductive line and a second conductive line adjacent to the first conductive line. A void is between the first and second conductive lines. A cap of insulating material is located above the void and defines an upper boundary of the void such that the void is further located between the base and the cap of insulating material. In some embodiments, one or more vias contacts an upper end of one or more of the conductive lines.

Abstract: Apparatus and methods for managing power consumption of a data-path in a computer system are provided, the data-path comprising a first port and a second port, the first port comprising a high-speed and the second port comprising a low-speed port. The disclosed method including connecting a device to the data-path, determining that the connected device is to communicate using the second port and turning off an active circuit associated with the first port of the data-path.

Abstract: Technologies for establishing and utilizing a decentralized cloud infrastructure using a plurality of mobile computing devices include broadcasting for the formation of the decentralized cloud computing and storage infrastructure and establishing wireless communications between the plurality of mobile computing devices. The plurality of mobile computing devices self-organize and cooperate with one another to establish a structured decentralized cloud infrastructure to expose and sharing resources, services, and/or applications for ad hoc or socially-driven decentralized, cloud computing purposes.

Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.